mirror of https://gitee.com/openkylin/linux.git
amd-xgbe: Make defines in xgbe.h unique
In order to avoid conflicts with other include files, add a prefix to the defines in xgbe.h. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Lendacky, Thomas
David S. Miller
parent
9b8d90b963
commit
d0a8ba6cba
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@ -131,7 +131,7 @@ static void xgbe_free_ring(struct xgbe_prv_data *pdata,
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if (ring->rdata) {
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for (i = 0; i < ring->rdesc_count; i++) {
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rdata = GET_DESC_DATA(ring, i);
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rdata = XGBE_GET_DESC_DATA(ring, i);
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xgbe_unmap_skb(pdata, rdata);
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}
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@ -256,7 +256,7 @@ static void xgbe_wrapper_tx_descriptor_init(struct xgbe_prv_data *pdata)
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rdesc_dma = ring->rdesc_dma;
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for (j = 0; j < ring->rdesc_count; j++) {
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rdata = GET_DESC_DATA(ring, j);
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rdata = XGBE_GET_DESC_DATA(ring, j);
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rdata->rdesc = rdesc;
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rdata->rdesc_dma = rdesc_dma;
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@ -298,7 +298,7 @@ static void xgbe_wrapper_rx_descriptor_init(struct xgbe_prv_data *pdata)
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rdesc_dma = ring->rdesc_dma;
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for (j = 0; j < ring->rdesc_count; j++) {
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rdata = GET_DESC_DATA(ring, j);
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rdata = XGBE_GET_DESC_DATA(ring, j);
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rdata->rdesc = rdesc;
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rdata->rdesc_dma = rdesc_dma;
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@ -392,7 +392,7 @@ static int xgbe_map_tx_skb(struct xgbe_channel *channel, struct sk_buff *skb)
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if ((tso && (packet->mss != ring->tx.cur_mss)) ||
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(vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag)))
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cur_index++;
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rdata = GET_DESC_DATA(ring, cur_index);
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rdata = XGBE_GET_DESC_DATA(ring, cur_index);
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if (tso) {
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DBGPR(" TSO packet\n");
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@ -413,12 +413,12 @@ static int xgbe_map_tx_skb(struct xgbe_channel *channel, struct sk_buff *skb)
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packet->length += packet->header_len;
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cur_index++;
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rdata = GET_DESC_DATA(ring, cur_index);
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rdata = XGBE_GET_DESC_DATA(ring, cur_index);
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}
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/* Map the (remainder of the) packet */
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for (datalen = skb_headlen(skb) - offset; datalen; ) {
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len = min_t(unsigned int, datalen, TX_MAX_BUF_SIZE);
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len = min_t(unsigned int, datalen, XGBE_TX_MAX_BUF_SIZE);
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skb_dma = dma_map_single(pdata->dev, skb->data + offset, len,
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DMA_TO_DEVICE);
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@ -437,7 +437,7 @@ static int xgbe_map_tx_skb(struct xgbe_channel *channel, struct sk_buff *skb)
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packet->length += len;
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cur_index++;
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rdata = GET_DESC_DATA(ring, cur_index);
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rdata = XGBE_GET_DESC_DATA(ring, cur_index);
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}
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for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
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@ -447,7 +447,8 @@ static int xgbe_map_tx_skb(struct xgbe_channel *channel, struct sk_buff *skb)
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offset = 0;
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for (datalen = skb_frag_size(frag); datalen; ) {
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len = min_t(unsigned int, datalen, TX_MAX_BUF_SIZE);
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len = min_t(unsigned int, datalen,
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XGBE_TX_MAX_BUF_SIZE);
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skb_dma = skb_frag_dma_map(pdata->dev, frag, offset,
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len, DMA_TO_DEVICE);
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@ -468,7 +469,7 @@ static int xgbe_map_tx_skb(struct xgbe_channel *channel, struct sk_buff *skb)
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packet->length += len;
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cur_index++;
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rdata = GET_DESC_DATA(ring, cur_index);
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rdata = XGBE_GET_DESC_DATA(ring, cur_index);
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}
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}
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@ -484,7 +485,7 @@ static int xgbe_map_tx_skb(struct xgbe_channel *channel, struct sk_buff *skb)
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err_out:
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while (start_index < cur_index) {
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rdata = GET_DESC_DATA(ring, start_index++);
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rdata = XGBE_GET_DESC_DATA(ring, start_index++);
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xgbe_unmap_skb(pdata, rdata);
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}
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@ -507,7 +508,7 @@ static void xgbe_realloc_skb(struct xgbe_channel *channel)
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ring->rx.realloc_index);
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for (i = 0; i < ring->dirty; i++) {
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rdata = GET_DESC_DATA(ring, ring->rx.realloc_index);
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rdata = XGBE_GET_DESC_DATA(ring, ring->rx.realloc_index);
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/* Reset rdata values */
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xgbe_unmap_skb(pdata, rdata);
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@ -766,7 +766,7 @@ static void xgbe_tx_desc_init(struct xgbe_channel *channel)
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/* Initialze all descriptors */
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for (i = 0; i < ring->rdesc_count; i++) {
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rdata = GET_DESC_DATA(ring, i);
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rdata = XGBE_GET_DESC_DATA(ring, i);
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rdesc = rdata->rdesc;
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/* Initialize Tx descriptor
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@ -791,7 +791,7 @@ static void xgbe_tx_desc_init(struct xgbe_channel *channel)
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XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1);
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/* Update the starting address of descriptor ring */
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rdata = GET_DESC_DATA(ring, start_index);
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rdata = XGBE_GET_DESC_DATA(ring, start_index);
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XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI,
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upper_32_bits(rdata->rdesc_dma));
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XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO,
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@ -848,7 +848,7 @@ static void xgbe_rx_desc_init(struct xgbe_channel *channel)
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/* Initialize all descriptors */
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for (i = 0; i < ring->rdesc_count; i++) {
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rdata = GET_DESC_DATA(ring, i);
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rdata = XGBE_GET_DESC_DATA(ring, i);
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rdesc = rdata->rdesc;
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/* Initialize Rx descriptor
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@ -882,14 +882,14 @@ static void xgbe_rx_desc_init(struct xgbe_channel *channel)
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XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1);
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/* Update the starting address of descriptor ring */
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rdata = GET_DESC_DATA(ring, start_index);
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rdata = XGBE_GET_DESC_DATA(ring, start_index);
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XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI,
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upper_32_bits(rdata->rdesc_dma));
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XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO,
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lower_32_bits(rdata->rdesc_dma));
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/* Update the Rx Descriptor Tail Pointer */
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rdata = GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1);
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rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1);
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XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
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lower_32_bits(rdata->rdesc_dma));
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@ -933,7 +933,7 @@ static void xgbe_pre_xmit(struct xgbe_channel *channel)
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if (tx_coalesce && !channel->tx_timer_active)
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ring->coalesce_count = 0;
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rdata = GET_DESC_DATA(ring, ring->cur);
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rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
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rdesc = rdata->rdesc;
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/* Create a context descriptor if this is a TSO packet */
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@ -977,7 +977,7 @@ static void xgbe_pre_xmit(struct xgbe_channel *channel)
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}
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ring->cur++;
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rdata = GET_DESC_DATA(ring, ring->cur);
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rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
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rdesc = rdata->rdesc;
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}
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@ -1034,7 +1034,7 @@ static void xgbe_pre_xmit(struct xgbe_channel *channel)
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for (i = ring->cur - start_index + 1; i < packet->rdesc_count; i++) {
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ring->cur++;
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rdata = GET_DESC_DATA(ring, ring->cur);
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rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
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rdesc = rdata->rdesc;
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/* Update buffer address */
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@ -1074,7 +1074,7 @@ static void xgbe_pre_xmit(struct xgbe_channel *channel)
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wmb();
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/* Set OWN bit for the first descriptor */
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rdata = GET_DESC_DATA(ring, start_index);
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rdata = XGBE_GET_DESC_DATA(ring, start_index);
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rdesc = rdata->rdesc;
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XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
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@ -1088,7 +1088,7 @@ static void xgbe_pre_xmit(struct xgbe_channel *channel)
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/* Issue a poll command to Tx DMA by writing address
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* of next immediate free descriptor */
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ring->cur++;
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rdata = GET_DESC_DATA(ring, ring->cur);
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rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
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XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO,
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lower_32_bits(rdata->rdesc_dma));
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@ -1117,7 +1117,7 @@ static int xgbe_dev_read(struct xgbe_channel *channel)
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DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur);
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rdata = GET_DESC_DATA(ring, ring->cur);
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rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
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rdesc = rdata->rdesc;
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/* Check for data availability */
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@ -1195,7 +1195,7 @@ static void xgbe_save_interrupt_status(struct xgbe_channel *channel,
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if (int_state == XGMAC_INT_STATE_SAVE) {
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channel->saved_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
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channel->saved_ier &= DMA_INTERRUPT_MASK;
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channel->saved_ier &= XGBE_DMA_INTERRUPT_MASK;
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} else {
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dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
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dma_ch_ier |= channel->saved_ier;
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@ -1275,7 +1275,7 @@ static int xgbe_disable_int(struct xgbe_channel *channel,
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xgbe_save_interrupt_status(channel, XGMAC_INT_STATE_SAVE);
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dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
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dma_ch_ier &= ~DMA_INTERRUPT_MASK;
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dma_ch_ier &= ~XGBE_DMA_INTERRUPT_MASK;
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XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
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break;
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default:
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@ -1342,23 +1342,23 @@ static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
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unsigned int arcache, awcache;
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arcache = 0;
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XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, DMA_ARCACHE_SETTING);
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XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, DMA_ARDOMAIN_SETTING);
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XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, DMA_ARCACHE_SETTING);
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XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, DMA_ARDOMAIN_SETTING);
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XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, DMA_ARCACHE_SETTING);
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XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, DMA_ARDOMAIN_SETTING);
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XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, XGBE_DMA_ARCACHE);
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XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, XGBE_DMA_ARDOMAIN);
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XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, XGBE_DMA_ARCACHE);
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XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, XGBE_DMA_ARDOMAIN);
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XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, XGBE_DMA_ARCACHE);
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XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, XGBE_DMA_ARDOMAIN);
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XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache);
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awcache = 0;
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XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, DMA_AWCACHE_SETTING);
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XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, DMA_AWDOMAIN_SETTING);
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XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, DMA_AWCACHE_SETTING);
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XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, DMA_AWDOMAIN_SETTING);
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XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, DMA_AWCACHE_SETTING);
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XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, DMA_AWDOMAIN_SETTING);
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XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, DMA_AWCACHE_SETTING);
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XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, DMA_AWDOMAIN_SETTING);
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XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, XGBE_DMA_AWCACHE);
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XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, XGBE_DMA_AWDOMAIN);
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XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, XGBE_DMA_AWCACHE);
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XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, XGBE_DMA_AWDOMAIN);
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XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, XGBE_DMA_AWCACHE);
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XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, XGBE_DMA_AWDOMAIN);
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XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, XGBE_DMA_AWCACHE);
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XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, XGBE_DMA_AWDOMAIN);
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XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache);
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}
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@ -1388,66 +1388,66 @@ static unsigned int xgbe_calculate_per_queue_fifo(unsigned long fifo_size,
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/* Calculate Tx/Rx fifo share per queue */
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switch (fifo_size) {
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case 0:
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q_fifo_size = FIFO_SIZE_B(128);
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q_fifo_size = XGBE_FIFO_SIZE_B(128);
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break;
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case 1:
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q_fifo_size = FIFO_SIZE_B(256);
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q_fifo_size = XGBE_FIFO_SIZE_B(256);
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break;
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case 2:
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q_fifo_size = FIFO_SIZE_B(512);
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q_fifo_size = XGBE_FIFO_SIZE_B(512);
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break;
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case 3:
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q_fifo_size = FIFO_SIZE_KB(1);
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q_fifo_size = XGBE_FIFO_SIZE_KB(1);
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break;
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case 4:
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q_fifo_size = FIFO_SIZE_KB(2);
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q_fifo_size = XGBE_FIFO_SIZE_KB(2);
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break;
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case 5:
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q_fifo_size = FIFO_SIZE_KB(4);
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q_fifo_size = XGBE_FIFO_SIZE_KB(4);
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break;
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case 6:
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q_fifo_size = FIFO_SIZE_KB(8);
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q_fifo_size = XGBE_FIFO_SIZE_KB(8);
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break;
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case 7:
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q_fifo_size = FIFO_SIZE_KB(16);
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q_fifo_size = XGBE_FIFO_SIZE_KB(16);
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break;
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case 8:
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q_fifo_size = FIFO_SIZE_KB(32);
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q_fifo_size = XGBE_FIFO_SIZE_KB(32);
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break;
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case 9:
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q_fifo_size = FIFO_SIZE_KB(64);
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q_fifo_size = XGBE_FIFO_SIZE_KB(64);
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break;
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case 10:
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q_fifo_size = FIFO_SIZE_KB(128);
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q_fifo_size = XGBE_FIFO_SIZE_KB(128);
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break;
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case 11:
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q_fifo_size = FIFO_SIZE_KB(256);
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q_fifo_size = XGBE_FIFO_SIZE_KB(256);
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break;
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}
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q_fifo_size = q_fifo_size / queue_count;
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/* Set the queue fifo size programmable value */
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if (q_fifo_size >= FIFO_SIZE_KB(256))
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if (q_fifo_size >= XGBE_FIFO_SIZE_KB(256))
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p_fifo = XGMAC_MTL_FIFO_SIZE_256K;
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else if (q_fifo_size >= FIFO_SIZE_KB(128))
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else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(128))
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p_fifo = XGMAC_MTL_FIFO_SIZE_128K;
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else if (q_fifo_size >= FIFO_SIZE_KB(64))
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else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(64))
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p_fifo = XGMAC_MTL_FIFO_SIZE_64K;
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else if (q_fifo_size >= FIFO_SIZE_KB(32))
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else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(32))
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p_fifo = XGMAC_MTL_FIFO_SIZE_32K;
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else if (q_fifo_size >= FIFO_SIZE_KB(16))
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else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(16))
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p_fifo = XGMAC_MTL_FIFO_SIZE_16K;
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else if (q_fifo_size >= FIFO_SIZE_KB(8))
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else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(8))
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p_fifo = XGMAC_MTL_FIFO_SIZE_8K;
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else if (q_fifo_size >= FIFO_SIZE_KB(4))
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else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(4))
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p_fifo = XGMAC_MTL_FIFO_SIZE_4K;
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else if (q_fifo_size >= FIFO_SIZE_KB(2))
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else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(2))
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p_fifo = XGMAC_MTL_FIFO_SIZE_2K;
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else if (q_fifo_size >= FIFO_SIZE_KB(1))
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else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(1))
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p_fifo = XGMAC_MTL_FIFO_SIZE_1K;
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else if (q_fifo_size >= FIFO_SIZE_B(512))
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else if (q_fifo_size >= XGBE_FIFO_SIZE_B(512))
|
||||
p_fifo = XGMAC_MTL_FIFO_SIZE_512;
|
||||
else if (q_fifo_size >= FIFO_SIZE_B(256))
|
||||
else if (q_fifo_size >= XGBE_FIFO_SIZE_B(256))
|
||||
p_fifo = XGMAC_MTL_FIFO_SIZE_256;
|
||||
|
||||
return p_fifo;
|
||||
|
|
|
|||
|
|
@ -144,9 +144,10 @@ static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
|
|||
}
|
||||
|
||||
rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
|
||||
if (rx_buf_size < RX_MIN_BUF_SIZE)
|
||||
rx_buf_size = RX_MIN_BUF_SIZE;
|
||||
rx_buf_size = (rx_buf_size + RX_BUF_ALIGN - 1) & ~(RX_BUF_ALIGN - 1);
|
||||
if (rx_buf_size < XGBE_RX_MIN_BUF_SIZE)
|
||||
rx_buf_size = XGBE_RX_MIN_BUF_SIZE;
|
||||
rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
|
||||
~(XGBE_RX_BUF_ALIGN - 1);
|
||||
|
||||
return rx_buf_size;
|
||||
}
|
||||
|
|
@ -446,7 +447,7 @@ static void xgbe_free_tx_skbuff(struct xgbe_prv_data *pdata)
|
|||
break;
|
||||
|
||||
for (j = 0; j < ring->rdesc_count; j++) {
|
||||
rdata = GET_DESC_DATA(ring, j);
|
||||
rdata = XGBE_GET_DESC_DATA(ring, j);
|
||||
desc_if->unmap_skb(pdata, rdata);
|
||||
}
|
||||
}
|
||||
|
|
@ -471,7 +472,7 @@ static void xgbe_free_rx_skbuff(struct xgbe_prv_data *pdata)
|
|||
break;
|
||||
|
||||
for (j = 0; j < ring->rdesc_count; j++) {
|
||||
rdata = GET_DESC_DATA(ring, j);
|
||||
rdata = XGBE_GET_DESC_DATA(ring, j);
|
||||
desc_if->unmap_skb(pdata, rdata);
|
||||
}
|
||||
}
|
||||
|
|
@ -726,14 +727,14 @@ static void xgbe_packet_info(struct xgbe_ring *ring, struct sk_buff *skb,
|
|||
|
||||
for (len = skb_headlen(skb); len;) {
|
||||
packet->rdesc_count++;
|
||||
len -= min_t(unsigned int, len, TX_MAX_BUF_SIZE);
|
||||
len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
|
||||
}
|
||||
|
||||
for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
|
||||
frag = &skb_shinfo(skb)->frags[i];
|
||||
for (len = skb_frag_size(frag); len; ) {
|
||||
packet->rdesc_count++;
|
||||
len -= min_t(unsigned int, len, TX_MAX_BUF_SIZE);
|
||||
len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1089,8 +1090,9 @@ static int xgbe_tx_poll(struct xgbe_channel *channel)
|
|||
|
||||
spin_lock_irqsave(&ring->lock, flags);
|
||||
|
||||
while ((processed < TX_DESC_MAX_PROC) && (ring->dirty < ring->cur)) {
|
||||
rdata = GET_DESC_DATA(ring, ring->dirty);
|
||||
while ((processed < XGBE_TX_DESC_MAX_PROC) &&
|
||||
(ring->dirty < ring->cur)) {
|
||||
rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
|
||||
rdesc = rdata->rdesc;
|
||||
|
||||
if (!hw_if->tx_complete(rdesc))
|
||||
|
|
@ -1109,7 +1111,7 @@ static int xgbe_tx_poll(struct xgbe_channel *channel)
|
|||
}
|
||||
|
||||
if ((ring->tx.queue_stopped == 1) &&
|
||||
(xgbe_tx_avail_desc(ring) > TX_DESC_MIN_FREE)) {
|
||||
(xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
|
||||
ring->tx.queue_stopped = 0;
|
||||
netif_wake_subqueue(netdev, channel->queue_index);
|
||||
}
|
||||
|
|
@ -1152,7 +1154,7 @@ static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
|
|||
cur_len = 0;
|
||||
|
||||
read_again:
|
||||
rdata = GET_DESC_DATA(ring, ring->cur);
|
||||
rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
|
||||
|
||||
if (hw_if->dev_read(channel))
|
||||
break;
|
||||
|
|
@ -1244,7 +1246,7 @@ static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
|
|||
|
||||
/* Update the Rx Tail Pointer Register with address of
|
||||
* the last cleaned entry */
|
||||
rdata = GET_DESC_DATA(ring, ring->rx.realloc_index - 1);
|
||||
rdata = XGBE_GET_DESC_DATA(ring, ring->rx.realloc_index - 1);
|
||||
XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
|
||||
lower_32_bits(rdata->rdesc_dma));
|
||||
}
|
||||
|
|
@ -1296,7 +1298,7 @@ void xgbe_dump_tx_desc(struct xgbe_ring *ring, unsigned int idx,
|
|||
struct xgbe_ring_desc *rdesc;
|
||||
|
||||
while (count--) {
|
||||
rdata = GET_DESC_DATA(ring, idx);
|
||||
rdata = XGBE_GET_DESC_DATA(ring, idx);
|
||||
rdesc = rdata->rdesc;
|
||||
DBGPR("TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
|
||||
(flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
|
||||
|
|
|
|||
|
|
@ -247,16 +247,16 @@ static int xgbe_probe(struct platform_device *pdev)
|
|||
mutex_init(&pdata->xpcs_mutex);
|
||||
|
||||
/* Set and validate the number of descriptors for a ring */
|
||||
BUILD_BUG_ON_NOT_POWER_OF_2(TX_DESC_CNT);
|
||||
pdata->tx_desc_count = TX_DESC_CNT;
|
||||
BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_TX_DESC_CNT);
|
||||
pdata->tx_desc_count = XGBE_TX_DESC_CNT;
|
||||
if (pdata->tx_desc_count & (pdata->tx_desc_count - 1)) {
|
||||
dev_err(dev, "tx descriptor count (%d) is not valid\n",
|
||||
pdata->tx_desc_count);
|
||||
ret = -EINVAL;
|
||||
goto err_io;
|
||||
}
|
||||
BUILD_BUG_ON_NOT_POWER_OF_2(RX_DESC_CNT);
|
||||
pdata->rx_desc_count = RX_DESC_CNT;
|
||||
BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_RX_DESC_CNT);
|
||||
pdata->rx_desc_count = XGBE_RX_DESC_CNT;
|
||||
if (pdata->rx_desc_count & (pdata->rx_desc_count - 1)) {
|
||||
dev_err(dev, "rx descriptor count (%d) is not valid\n",
|
||||
pdata->rx_desc_count);
|
||||
|
|
|
|||
|
|
@ -128,22 +128,25 @@
|
|||
#define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
|
||||
|
||||
/* Descriptor related defines */
|
||||
#define TX_DESC_CNT 512
|
||||
#define TX_DESC_MIN_FREE (TX_DESC_CNT >> 3)
|
||||
#define TX_DESC_MAX_PROC (TX_DESC_CNT >> 1)
|
||||
#define RX_DESC_CNT 512
|
||||
#define XGBE_TX_DESC_CNT 512
|
||||
#define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
|
||||
#define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
|
||||
#define XGBE_RX_DESC_CNT 512
|
||||
|
||||
#define TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
|
||||
#define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
|
||||
|
||||
#define RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
|
||||
#define RX_BUF_ALIGN 64
|
||||
#define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
|
||||
#define XGBE_RX_BUF_ALIGN 64
|
||||
|
||||
#define XGBE_MAX_DMA_CHANNELS 16
|
||||
#define DMA_ARDOMAIN_SETTING 0x2
|
||||
#define DMA_ARCACHE_SETTING 0xb
|
||||
#define DMA_AWDOMAIN_SETTING 0x2
|
||||
#define DMA_AWCACHE_SETTING 0x7
|
||||
#define DMA_INTERRUPT_MASK 0x31c7
|
||||
|
||||
/* DMA cache settings - Outer sharable, write-back, write-allocate */
|
||||
#define XGBE_DMA_ARDOMAIN 0x2
|
||||
#define XGBE_DMA_ARCACHE 0xb
|
||||
#define XGBE_DMA_AWDOMAIN 0x2
|
||||
#define XGBE_DMA_AWCACHE 0x7
|
||||
|
||||
#define XGBE_DMA_INTERRUPT_MASK 0x31c7
|
||||
|
||||
#define XGMAC_MIN_PACKET 60
|
||||
#define XGMAC_STD_PACKET_MTU 1500
|
||||
|
|
@ -151,10 +154,6 @@
|
|||
#define XGMAC_JUMBO_PACKET_MTU 9000
|
||||
#define XGMAC_MAX_JUMBO_PACKET 9018
|
||||
|
||||
#define MAX_MULTICAST_LIST 14
|
||||
#define TX_FLAGS_IP_PKT 0x00000001
|
||||
#define TX_FLAGS_TCP_PKT 0x00000002
|
||||
|
||||
/* MDIO bus phy name */
|
||||
#define XGBE_PHY_NAME "amd_xgbe_phy"
|
||||
#define XGBE_PRTAD 0
|
||||
|
|
@ -163,18 +162,18 @@
|
|||
#define XGMAC_DRIVER_CONTEXT 1
|
||||
#define XGMAC_IOCTL_CONTEXT 2
|
||||
|
||||
#define FIFO_SIZE_B(x) (x)
|
||||
#define FIFO_SIZE_KB(x) (x * 1024)
|
||||
#define XGBE_FIFO_SIZE_B(x) (x)
|
||||
#define XGBE_FIFO_SIZE_KB(x) (x * 1024)
|
||||
|
||||
#define XGBE_TC_CNT 2
|
||||
|
||||
/* Helper macro for descriptor handling
|
||||
* Always use GET_DESC_DATA to access the descriptor data
|
||||
* Always use XGBE_GET_DESC_DATA to access the descriptor data
|
||||
* since the index is free-running and needs to be and-ed
|
||||
* with the descriptor count value of the ring to index to
|
||||
* the proper descriptor data.
|
||||
*/
|
||||
#define GET_DESC_DATA(_ring, _idx) \
|
||||
#define XGBE_GET_DESC_DATA(_ring, _idx) \
|
||||
((_ring)->rdata + \
|
||||
((_idx) & ((_ring)->rdesc_count - 1)))
|
||||
|
||||
|
|
@ -219,7 +218,7 @@ struct xgbe_ring_desc {
|
|||
|
||||
/* Structure used to hold information related to the descriptor
|
||||
* and the packet associated with the descriptor (always use
|
||||
* use the GET_DESC_DATA macro to access this data from the ring)
|
||||
* use the XGBE_GET_DESC_DATA macro to access this data from the ring)
|
||||
*/
|
||||
struct xgbe_ring_data {
|
||||
struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
|
||||
|
|
@ -250,7 +249,7 @@ struct xgbe_ring {
|
|||
unsigned int rdesc_count;
|
||||
|
||||
/* Array of descriptor data corresponding the descriptor memory
|
||||
* (always use the GET_DESC_DATA macro to access this data)
|
||||
* (always use the XGBE_GET_DESC_DATA macro to access this data)
|
||||
*/
|
||||
struct xgbe_ring_data *rdata;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue