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Allwinner DT changes for 5.1, take 2 

Our usual bunch of DT changes for the Allwinner arm SoCs:
   - LCD support for the Q8 A13 tablets
   - GMAC support for the A80
   - PMIC power supplies for the A83t
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Merge tag 'sunxi-dt-for-5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt

Allwinner DT changes for 5.1, take 2

Our usual bunch of DT changes for the Allwinner arm SoCs:
  - LCD support for the Q8 A13 tablets
  - GMAC support for the A80
  - PMIC power supplies for the A83t

* tag 'sunxi-dt-for-5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  ARM: dts: sun8i: a83t: Enable PMIC power supplies on various boards
  ARM: dts: sun9i: cubieboard4: Enable GMAC
  ARM: dts: sun9i: a80-optimus: Enable GMAC
  ARM: dts: sun9i: Add A80 GMAC RGMII pinmux setting
  ARM: dts: sun9i: Add A80 GMAC gigabit ethernet controller node
  ARM: dts: sun9i: Add GMAC clock node
  ARM: dts: sun9i: cubieboard4: Add GPIO pin-bank regulator supplies
  ARM: dts: sun9i: a80-optimus: Add GPIO pin-bank regulator supplies
  ARM: dts: sun9i: a80-optimus: Add node for AXP809's unused dc1sw regulator
  ARM: dts: sun5i: q8-tablet: Use bananapi,s070wv20-ct16 panel compatible
  ARM: dts: sun5i: q8-tablet: Add LCD Panel power supply
  ARM: dts: sun5i: q8-tablet: Add LCD Panel enable GPIO
  ARM: dts: sun5i: q8-tablet: Move panel properties to correct node level
  ARM: dts: sun5i: Add backlight GPIO for reference design tablet

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2019-02-15 15:42:14 +01:00
parent 175a366f70 185401e1dd
commit d0bc18830d
8 changed files with 172 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
arch/arm/boot/dts/sun5i-a13-q8-tablet.dts
View File

@ -49,14 +49,15 @@ / {
compatible = "allwinner,q8-a13", "allwinner,sun5i-a13";
panel: panel {
compatible = "urt,umsh-8596md-t", "simple-panel";
compatible = "bananapi,s070wv20-ct16", "simple-panel";
power-supply = <&reg_vcc3v3>;
enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */
backlight = <&backlight>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
/* TODO: lcd panel uses axp gpio0 as enable pin */
backlight = <&backlight>;
#address-cells = <1>;
#size-cells = <0>;

2
arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
View File

@ -54,7 +54,7 @@ backlight: backlight {
pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
/* TODO: backlight uses axp gpio1 as enable pin */
enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; /* AXP GPIO1 */
};
chosen {

4
arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
View File

@ -154,6 +154,10 @@ ac100_rtc: rtc {
#include "axp81x.dtsi"
&ac_power_supply {
status = "okay";
};
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;

8
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
View File

@ -237,6 +237,14 @@ ac100_rtc: rtc {
#include "axp81x.dtsi"
&ac_power_supply {
status = "okay";
};
&battery_power_supply {
status = "okay";
};
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;

8
arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
View File

@ -247,6 +247,14 @@ ac100_rtc: rtc {
#include "axp81x.dtsi"
&ac_power_supply {
status = "okay";
};
&battery_power_supply {
status = "okay";
};
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;

44
arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
View File

@ -133,6 +133,19 @@ &de {
status = "okay";
};
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "rgmii";
phy-supply = <&reg_cldo1>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
@ -183,10 +196,26 @@ &osc32k {
clocks = <&ac100_rtc 0>;
};
&pio {
vcc-pa-supply = <&reg_ldo_io1>;
vcc-pb-supply = <&reg_aldo2>;
vcc-pc-supply = <&reg_dcdc1>;
vcc-pd-supply = <&reg_dc1sw>;
vcc-pe-supply = <&reg_eldo2>;
vcc-pf-supply = <&reg_dcdc1>;
vcc-pg-supply = <&reg_ldo_io0>;
vcc-ph-supply = <&reg_dcdc1>;
};
&r_ir {
status = "okay";
};
&r_pio {
vcc-pl-supply = <&reg_dldo2>;
vcc-pm-supply = <&reg_eldo3>;
};
&r_rsb {
status = "okay";
@ -217,6 +246,10 @@ aldo3 {
/* unused */
};
reg_dc1sw: dc1sw {
regulator-name = "vcc-pd";
};
reg_dc5ldo: dc5ldo {
regulator-always-on;
regulator-min-microvolt = <800000>;
@ -271,7 +304,6 @@ reg_dldo1: dldo1 {
};
reg_dldo2: dldo2 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-pl";
@ -290,14 +322,12 @@ reg_eldo2: eldo2 {
};
reg_eldo3: eldo3 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-pm-codec-io1";
};
reg_ldo_io0: ldo_io0 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-pg";
@ -385,6 +415,14 @@ reg_cldo1: cldo1 {
*/
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
/*
* The PHY requires 20ms after all voltages
* are applied until core logic is ready and
* 30ms after the reset pin is de-asserted.
* Set a 100ms delay to account for PMIC
* ramp time and board traces.
*/
regulator-enable-ramp-delay = <100000>;
regulator-name = "vcc-gmac-phy";
};

44
arch/arm/boot/dts/sun9i-a80-optimus.dts
View File

@ -120,6 +120,19 @@ &ehci2 {
status = "okay";
};
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "rgmii";
phy-supply = <&reg_cldo1>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
@ -172,10 +185,26 @@ &osc32k {
clocks = <&ac100_rtc 0>;
};
&pio {
vcc-pa-supply = <&reg_ldo_io1>;
vcc-pb-supply = <&reg_aldo2>;
vcc-pc-supply = <&reg_dcdc1>;
vcc-pd-supply = <&reg_dcdc1>;
vcc-pe-supply = <&reg_eldo2>;
vcc-pf-supply = <&reg_dcdc1>;
vcc-pg-supply = <&reg_ldo_io0>;
vcc-ph-supply = <&reg_dcdc1>;
};
&r_ir {
status = "okay";
};
&r_pio {
vcc-pl-supply = <&reg_dldo2>;
vcc-pm-supply = <&reg_eldo3>;
};
&r_rsb {
status = "okay";
@ -213,6 +242,10 @@ reg_dc5ldo: dc5ldo {
regulator-name = "vdd-cpus-09-usbh";
};
dc1sw {
/* unused */
};
reg_dcdc1: dcdc1 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
@ -260,7 +293,6 @@ reg_dldo1: dldo1 {
};
reg_dldo2: dldo2 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-pl";
@ -279,14 +311,12 @@ reg_eldo2: eldo2 {
};
reg_eldo3: eldo3 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-pm-codec-io1";
};
reg_ldo_io0: ldo_io0 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-pg";
@ -374,6 +404,14 @@ reg_cldo1: cldo1 {
*/
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
/*
* The PHY requires 20ms after all voltages
* are applied until core logic is ready and
* 30ms after the reset pin is de-asserted.
* Set a 100ms delay to account for PMIC
* ramp time and board traces.
*/
regulator-enable-ramp-delay = <100000>;
regulator-name = "vcc-gmac-phy";
};

65
arch/arm/boot/dts/sun9i-a80.dtsi
View File

@ -56,6 +56,10 @@ / {
#size-cells = <2>;
interrupt-parent = <&gic>;
aliases {
ethernet0 = &gmac;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -183,6 +187,37 @@ osc32k: clk-32k {
clock-output-names = "osc32k";
};
/*
* The following two are dummy clocks, placeholders
* used in the gmac_tx clock. The gmac driver will
* choose one parent depending on the PHY interface
* mode, using clk_set_rate auto-reparenting.
*
* The actual TX clock rate is not controlled by the
* gmac_tx clock.
*/
mii_phy_tx_clk: mii_phy_tx_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "mii_phy_tx";
};
gmac_int_tx_clk: gmac_int_tx_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_int_tx";
};
gmac_tx_clk: clk@800030 {
#clock-cells = <0>;
compatible = "allwinner,sun7i-a20-gmac-clk";
reg = <0x00800030 0x4>;
clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
clock-output-names = "gmac_tx";
};
cpus_clk: clk@8001410 {
compatible = "allwinner,sun9i-a80-cpus-clk";
reg = <0x08001410 0x4>;
@ -283,6 +318,23 @@ smp-sram@1000 {
};
};
gmac: ethernet@830000 {
compatible = "allwinner,sun7i-a20-gmac";
reg = <0x00830000 0x1054>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
clock-names = "stmmaceth", "allwinner_gmac_tx";
resets = <&ccu RST_BUS_GMAC>;
reset-names = "stmmaceth";
snps,pbl = <2>;
snps,fixed-burst;
snps,force_sf_dma_mode;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
ehci0: usb@a00000 {
compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
reg = <0x00a00000 0x100>;
@ -948,6 +1000,19 @@ pio: pinctrl@6000800 {
#size-cells = <0>;
#gpio-cells = <3>;
gmac_rgmii_pins: gmac-rgmii-pins {
allwinner,pins = "PA0", "PA1", "PA2", "PA3",
"PA4", "PA5", "PA7", "PA8",
"PA9", "PA10", "PA12", "PA13",
"PA15", "PA16", "PA17";
allwinner,function = "gmac";
/*
* data lines in RGMII mode use DDR mode
* and need a higher signal drive strength
*/
drive-strength = <40>;
};
i2c3_pins: i2c3-pins {
pins = "PG10", "PG11";
function = "i2c3";