mirror of https://gitee.com/openkylin/linux.git
drm/i915/skl: Log the order in which we flush the pipes in the WM code
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -3536,11 +3536,14 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv,
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* We need to sequence the re-allocation: C, B, A (and not B, C, A).
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* We need to sequence the re-allocation: C, B, A (and not B, C, A).
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*/
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*/
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static void skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
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static void
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skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
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{
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{
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struct drm_device *dev = dev_priv->dev;
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struct drm_device *dev = dev_priv->dev;
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int plane;
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int plane;
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DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
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for_each_plane(pipe, plane) {
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for_each_plane(pipe, plane) {
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I915_WRITE(PLANE_SURF(pipe, plane),
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I915_WRITE(PLANE_SURF(pipe, plane),
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I915_READ(PLANE_SURF(pipe, plane)));
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I915_READ(PLANE_SURF(pipe, plane)));
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@ -3591,7 +3594,7 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
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if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
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if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
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continue;
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continue;
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skl_wm_flush_pipe(dev_priv, pipe);
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skl_wm_flush_pipe(dev_priv, pipe, 1);
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intel_wait_for_vblank(dev, pipe);
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intel_wait_for_vblank(dev, pipe);
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reallocated[pipe] = true;
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reallocated[pipe] = true;
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@ -3616,7 +3619,7 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
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if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
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if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
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skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
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skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
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skl_wm_flush_pipe(dev_priv, pipe);
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skl_wm_flush_pipe(dev_priv, pipe, 2);
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intel_wait_for_vblank(dev, pipe);
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intel_wait_for_vblank(dev, pipe);
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}
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}
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@ -3642,7 +3645,7 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
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if (reallocated[pipe])
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if (reallocated[pipe])
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continue;
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continue;
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skl_wm_flush_pipe(dev_priv, pipe);
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skl_wm_flush_pipe(dev_priv, pipe, 3);
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}
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}
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}
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}
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