mirror of https://gitee.com/openkylin/linux.git
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Vr41xx: Fix after GENERIC_HARDIRQS_NO__DO_IRQ change [MIPS] SMTC: Instant IPI replay.
This commit is contained in:
Linus Torvalds
commit
d227e87e6c
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@ -1568,6 +1568,20 @@ config MIPS_MT_FPAFF
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depends on MIPS_MT
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default y
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config MIPS_MT_SMTC_INSTANT_REPLAY
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bool "Low-latency Dispatch of Deferred SMTC IPIs"
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depends on MIPS_MT_SMTC
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default y
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help
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SMTC pseudo-interrupts between TCs are deferred and queued
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if the target TC is interrupt-inhibited (IXMT). In the first
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SMTC prototypes, these queued IPIs were serviced on return
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to user mode, or on entry into the kernel idle loop. The
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INSTANT_REPLAY option dispatches them as part of local_irq_restore()
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processing, which adds runtime overhead (hence the option to turn
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it off), but ensures that IPIs are handled promptly even under
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heavy I/O interrupt load.
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config MIPS_VPE_LOADER_TOM
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bool "Load VPE program into memory hidden from linux"
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depends on MIPS_VPE_LOADER
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@ -1017,6 +1017,33 @@ void setup_cross_vpe_interrupts(void)
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* SMTC-specific hacks invoked from elsewhere in the kernel.
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*/
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void smtc_ipi_replay(void)
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{
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/*
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* To the extent that we've ever turned interrupts off,
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* we may have accumulated deferred IPIs. This is subtle.
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* If we use the smtc_ipi_qdepth() macro, we'll get an
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* exact number - but we'll also disable interrupts
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* and create a window of failure where a new IPI gets
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* queued after we test the depth but before we re-enable
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* interrupts. So long as IXMT never gets set, however,
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* we should be OK: If we pick up something and dispatch
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* it here, that's great. If we see nothing, but concurrent
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* with this operation, another TC sends us an IPI, IXMT
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* is clear, and we'll handle it as a real pseudo-interrupt
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* and not a pseudo-pseudo interrupt.
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*/
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if (IPIQ[smp_processor_id()].depth > 0) {
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struct smtc_ipi *pipi;
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extern void self_ipi(struct smtc_ipi *);
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while ((pipi = smtc_ipi_dq(&IPIQ[smp_processor_id()]))) {
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self_ipi(pipi);
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smtc_cpu_stats[smp_processor_id()].selfipis++;
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}
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}
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}
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void smtc_idle_loop_hook(void)
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{
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#ifdef SMTC_IDLE_HOOK_DEBUG
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@ -1113,29 +1140,14 @@ void smtc_idle_loop_hook(void)
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if (pdb_msg != &id_ho_db_msg[0])
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printk("CPU%d: %s", smp_processor_id(), id_ho_db_msg);
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#endif /* SMTC_IDLE_HOOK_DEBUG */
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/*
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* To the extent that we've ever turned interrupts off,
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* we may have accumulated deferred IPIs. This is subtle.
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* If we use the smtc_ipi_qdepth() macro, we'll get an
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* exact number - but we'll also disable interrupts
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* and create a window of failure where a new IPI gets
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* queued after we test the depth but before we re-enable
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* interrupts. So long as IXMT never gets set, however,
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* we should be OK: If we pick up something and dispatch
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* it here, that's great. If we see nothing, but concurrent
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* with this operation, another TC sends us an IPI, IXMT
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* is clear, and we'll handle it as a real pseudo-interrupt
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* and not a pseudo-pseudo interrupt.
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*/
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if (IPIQ[smp_processor_id()].depth > 0) {
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struct smtc_ipi *pipi;
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extern void self_ipi(struct smtc_ipi *);
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if ((pipi = smtc_ipi_dq(&IPIQ[smp_processor_id()])) != NULL) {
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self_ipi(pipi);
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smtc_cpu_stats[smp_processor_id()].selfipis++;
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}
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}
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/*
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* Replay any accumulated deferred IPIs. If "Instant Replay"
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* is in use, there should never be any.
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*/
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#ifndef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY
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smtc_ipi_replay();
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#endif /* CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY */
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}
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void smtc_soft_dump(void)
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@ -1,7 +1,7 @@
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/*
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* Interrupt handing routines for NEC VR4100 series.
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*
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* Copyright (C) 2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
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* Copyright (C) 2005-2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -73,13 +73,19 @@ static void irq_dispatch(unsigned int irq)
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if (cascade->get_irq != NULL) {
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unsigned int source_irq = irq;
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desc = irq_desc + source_irq;
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desc->chip->ack(source_irq);
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if (desc->chip->mask_ack)
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desc->chip->mask_ack(source_irq);
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else {
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desc->chip->mask(source_irq);
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desc->chip->ack(source_irq);
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}
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irq = cascade->get_irq(irq);
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if (irq < 0)
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atomic_inc(&irq_err_count);
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else
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irq_dispatch(irq);
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desc->chip->end(source_irq);
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if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
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desc->chip->unmask(source_irq);
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} else
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do_IRQ(irq);
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}
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@ -3,7 +3,7 @@
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*
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* Copyright (C) 2002 MontaVista Software Inc.
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* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
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* Copyright (C) 2003-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
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* Copyright (C) 2003-2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -125,30 +125,17 @@ static inline uint16_t giu_clear(uint16_t offset, uint16_t clear)
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return data;
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}
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static unsigned int startup_giuint_low_irq(unsigned int irq)
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static void ack_giuint_low(unsigned int irq)
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{
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unsigned int pin;
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pin = GPIO_PIN_OF_IRQ(irq);
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giu_write(GIUINTSTATL, 1 << pin);
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giu_set(GIUINTENL, 1 << pin);
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return 0;
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giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(irq));
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}
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static void shutdown_giuint_low_irq(unsigned int irq)
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static void mask_giuint_low(unsigned int irq)
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{
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giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
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}
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static void enable_giuint_low_irq(unsigned int irq)
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{
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giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
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}
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#define disable_giuint_low_irq shutdown_giuint_low_irq
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static void ack_giuint_low_irq(unsigned int irq)
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static void mask_ack_giuint_low(unsigned int irq)
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{
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unsigned int pin;
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@ -157,46 +144,30 @@ static void ack_giuint_low_irq(unsigned int irq)
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giu_write(GIUINTSTATL, 1 << pin);
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}
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static void end_giuint_low_irq(unsigned int irq)
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static void unmask_giuint_low(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
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giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
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}
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static struct hw_interrupt_type giuint_low_irq_type = {
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.typename = "GIUINTL",
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.startup = startup_giuint_low_irq,
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.shutdown = shutdown_giuint_low_irq,
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.enable = enable_giuint_low_irq,
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.disable = disable_giuint_low_irq,
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.ack = ack_giuint_low_irq,
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.end = end_giuint_low_irq,
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static struct irq_chip giuint_low_irq_chip = {
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.name = "GIUINTL",
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.ack = ack_giuint_low,
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.mask = mask_giuint_low,
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.mask_ack = mask_ack_giuint_low,
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.unmask = unmask_giuint_low,
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};
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static unsigned int startup_giuint_high_irq(unsigned int irq)
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static void ack_giuint_high(unsigned int irq)
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{
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unsigned int pin;
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pin = GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET;
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giu_write(GIUINTSTATH, 1 << pin);
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giu_set(GIUINTENH, 1 << pin);
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return 0;
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giu_write(GIUINTSTATH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
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}
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static void shutdown_giuint_high_irq(unsigned int irq)
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static void mask_giuint_high(unsigned int irq)
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{
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giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
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}
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static void enable_giuint_high_irq(unsigned int irq)
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{
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giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
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}
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#define disable_giuint_high_irq shutdown_giuint_high_irq
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static void ack_giuint_high_irq(unsigned int irq)
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static void mask_ack_giuint_high(unsigned int irq)
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{
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unsigned int pin;
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@ -205,20 +176,17 @@ static void ack_giuint_high_irq(unsigned int irq)
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giu_write(GIUINTSTATH, 1 << pin);
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}
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static void end_giuint_high_irq(unsigned int irq)
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static void unmask_giuint_high(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
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giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
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}
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static struct hw_interrupt_type giuint_high_irq_type = {
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.typename = "GIUINTH",
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.startup = startup_giuint_high_irq,
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.shutdown = shutdown_giuint_high_irq,
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.enable = enable_giuint_high_irq,
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.disable = disable_giuint_high_irq,
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.ack = ack_giuint_high_irq,
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.end = end_giuint_high_irq,
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static struct irq_chip giuint_high_irq_chip = {
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.name = "GIUINTH",
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.ack = ack_giuint_high,
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.mask = mask_giuint_high,
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.mask_ack = mask_ack_giuint_high,
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.unmask = unmask_giuint_high,
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};
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static int giu_get_irq(unsigned int irq)
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@ -282,9 +250,15 @@ void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_
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break;
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}
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}
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set_irq_chip_and_handler(GIU_IRQ(pin),
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&giuint_low_irq_chip,
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handle_edge_irq);
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} else {
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giu_clear(GIUINTTYPL, mask);
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giu_clear(GIUINTHTSELL, mask);
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set_irq_chip_and_handler(GIU_IRQ(pin),
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&giuint_low_irq_chip,
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handle_level_irq);
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}
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giu_write(GIUINTSTATL, mask);
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} else if (pin < GIUINT_HIGH_MAX) {
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@ -311,9 +285,15 @@ void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_
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break;
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}
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}
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set_irq_chip_and_handler(GIU_IRQ(pin),
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&giuint_high_irq_chip,
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handle_edge_irq);
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} else {
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giu_clear(GIUINTTYPH, mask);
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giu_clear(GIUINTHTSELH, mask);
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set_irq_chip_and_handler(GIU_IRQ(pin),
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&giuint_high_irq_chip,
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handle_level_irq);
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}
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giu_write(GIUINTSTATH, mask);
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}
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@ -617,10 +597,11 @@ static const struct file_operations gpio_fops = {
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static int __devinit giu_probe(struct platform_device *dev)
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{
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unsigned long start, size, flags = 0;
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unsigned int nr_pins = 0;
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unsigned int nr_pins = 0, trigger, i, pin;
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struct resource *res1, *res2 = NULL;
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void *base;
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int retval, i;
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struct irq_chip *chip;
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int retval;
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switch (current_cpu_data.cputype) {
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case CPU_VR4111:
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@ -688,11 +669,20 @@ static int __devinit giu_probe(struct platform_device *dev)
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giu_write(GIUINTENL, 0);
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giu_write(GIUINTENH, 0);
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trigger = giu_read(GIUINTTYPH) << 16;
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trigger |= giu_read(GIUINTTYPL);
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for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
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if (i < GIU_IRQ(GIUINT_HIGH_OFFSET))
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irq_desc[i].chip = &giuint_low_irq_type;
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pin = GPIO_PIN_OF_IRQ(i);
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if (pin < GIUINT_HIGH_OFFSET)
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chip = &giuint_low_irq_chip;
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else
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irq_desc[i].chip = &giuint_high_irq_type;
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chip = &giuint_high_irq_chip;
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if (trigger & (1 << pin))
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set_irq_chip_and_handler(i, chip, handle_edge_irq);
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else
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set_irq_chip_and_handler(i, chip, handle_level_irq);
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}
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return cascade_irq(GIUINT_IRQ, giu_get_irq);
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@ -15,6 +15,27 @@
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#include <asm/hazards.h>
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/*
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* CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY does prompt replay of deferred IPIs,
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* at the cost of branch and call overhead on each local_irq_restore()
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*/
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#ifdef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY
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extern void smtc_ipi_replay(void);
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#define irq_restore_epilog(flags) \
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do { \
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if (!(flags & 0x0400)) \
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smtc_ipi_replay(); \
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} while (0)
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#else
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#define irq_restore_epilog(ignore) do { } while (0)
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#endif /* CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY */
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__asm__ (
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" .macro raw_local_irq_enable \n"
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" .set push \n"
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@ -193,6 +214,7 @@ do { \
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: "=r" (__tmp1) \
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: "0" (flags) \
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: "memory"); \
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irq_restore_epilog(flags); \
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} while(0)
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static inline int raw_irqs_disabled_flags(unsigned long flags)
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