mirror of https://gitee.com/openkylin/linux.git
ARM: ti81xx: Add hwmod boilerplate for all GPIO and SPI peripherals
GPIO3/4 and MCSPI2/3/4 are now present. Lightly tested on am3874 platform. Signed-off-by: Graeme Smecher <gsmecher@threespeedlogic.com> [tony@atomide.com: split to apply hwmod and dts changes separately] Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -539,6 +539,58 @@ static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
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{ .role = "dbclk", .clk = "sysclk18_ck" },
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};
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static struct omap_hwmod dm81xx_gpio3_hwmod = {
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.name = "gpio3",
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.clkdm_name = "alwon_l3s_clkdm",
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.class = &dm81xx_gpio_hwmod_class,
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.main_clk = "sysclk6_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.opt_clks = gpio3_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
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};
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static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio3 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm81xx_gpio3_hwmod,
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.clk = "sysclk6_ck",
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
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{ .role = "dbclk", .clk = "sysclk18_ck" },
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};
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static struct omap_hwmod dm81xx_gpio4_hwmod = {
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.name = "gpio4",
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.clkdm_name = "alwon_l3s_clkdm",
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.class = &dm81xx_gpio_hwmod_class,
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.main_clk = "sysclk6_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.opt_clks = gpio4_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
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};
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static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio4 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm81xx_gpio4_hwmod,
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.clk = "sysclk6_ck",
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = {
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.rev_offs = 0x0,
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.sysc_offs = 0x10,
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@ -1133,6 +1185,45 @@ static struct omap_hwmod dm81xx_mcspi1_hwmod = {
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.class = &dm816x_mcspi_class,
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};
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static struct omap_hwmod dm81xx_mcspi2_hwmod = {
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.name = "mcspi2",
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.clkdm_name = "alwon_l3s_clkdm",
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.main_clk = "sysclk10_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.class = &dm816x_mcspi_class,
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};
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static struct omap_hwmod dm81xx_mcspi3_hwmod = {
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.name = "mcspi3",
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.clkdm_name = "alwon_l3s_clkdm",
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.main_clk = "sysclk10_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.class = &dm816x_mcspi_class,
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};
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static struct omap_hwmod dm81xx_mcspi4_hwmod = {
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.name = "mcspi4",
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.clkdm_name = "alwon_l3s_clkdm",
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.main_clk = "sysclk10_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.class = &dm816x_mcspi_class,
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};
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static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm81xx_mcspi1_hwmod,
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@ -1140,6 +1231,27 @@ static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi2 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm81xx_mcspi2_hwmod,
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.clk = "sysclk6_ck",
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi3 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm81xx_mcspi3_hwmod,
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.clk = "sysclk6_ck",
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi4 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm81xx_mcspi4_hwmod,
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.clk = "sysclk6_ck",
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = {
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.rev_offs = 0x000,
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.sysc_offs = 0x010,
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@ -1378,8 +1490,13 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
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&dm81xx_l4_ls__i2c2,
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&dm81xx_l4_ls__gpio1,
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&dm81xx_l4_ls__gpio2,
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&dm81xx_l4_ls__gpio3,
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&dm81xx_l4_ls__gpio4,
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&dm81xx_l4_ls__elm,
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&dm81xx_l4_ls__mcspi1,
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&dm81xx_l4_ls__mcspi2,
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&dm81xx_l4_ls__mcspi3,
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&dm81xx_l4_ls__mcspi4,
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&dm814x_l4_ls__mmc1,
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&dm814x_l4_ls__mmc2,
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&ti81xx_l4_ls__rtc,
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