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ARM: dts: sun7i: Add CSI0 controller 

The CSI controller embedded in the A20 can be supported by our new driver.
Let's add it to our DT.

Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This commit is contained in:
Maxime Ripard 2019-08-22 10:21:15 +02:00
parent 94f68f3a4b
commit d2b9c64443
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GPG Key ID: E3EF0D6F671851C5
1 changed files with 25 additions and 0 deletions
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25
arch/arm/boot/dts/sun7i-a20.dtsi
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@ -376,6 +376,17 @@ spi1: spi@1c06000 {
num-cs = <1>; num-cs = <1>;
}; };
csi0: csi@1c09000 {
compatible = "allwinner,sun7i-a20-csi0";
reg = <0x01c09000 0x1000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>,
<&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
clock-names = "bus", "mod", "isp", "ram";
resets = <&ccu RST_CSI0>;
status = "disabled";
};
emac: ethernet@1c0b000 { emac: ethernet@1c0b000 {
compatible = "allwinner,sun4i-a10-emac"; compatible = "allwinner,sun4i-a10-emac";
reg = <0x01c0b000 0x1000>; reg = <0x01c0b000 0x1000>;
@ -774,6 +785,20 @@ clk_out_b_pin: clk-out-b-pin {
function = "clk_out_b"; function = "clk_out_b";
}; };
/omit-if-no-ref/
csi0_8bits_pins: csi-8bits-pins {
pins = "PE0", "PE2", "PE3", "PE4", "PE5",
"PE6", "PE7", "PE8", "PE9", "PE10",
"PE11";
function = "csi0";
};
/omit-if-no-ref/
csi0_clk_pin: csi-clk-pin {
pins = "PE1";
function = "csi0";
};
/omit-if-no-ref/ /omit-if-no-ref/
emac_pa_pins: emac-pa-pins { emac_pa_pins: emac-pa-pins {
pins = "PA0", "PA1", "PA2", pins = "PA0", "PA1", "PA2",