mirror of https://gitee.com/openkylin/linux.git
ixgbe: Use new methods for PHY access
Now x550em_a devices will use a new method for PHY access that will get the firmware token for each access. Signed-off-by: Mark Rustad <mark.d.rustad@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -2548,6 +2548,57 @@ static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
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ixgbe_release_swfw_sync_X540(hw, hmask);
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}
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/**
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* ixgbe_read_phy_reg_x550a - Reads specified PHY register
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* @hw: pointer to hardware structure
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* @reg_addr: 32 bit address of PHY register to read
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* @phy_data: Pointer to read data from PHY register
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*
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* Reads a value from a specified PHY register using the SWFW lock and PHY
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* Token. The PHY Token is needed since the MDIO is shared between to MAC
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* instances.
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*/
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static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
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u32 device_type, u16 *phy_data)
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{
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u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
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s32 status;
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if (hw->mac.ops.acquire_swfw_sync(hw, mask))
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return IXGBE_ERR_SWFW_SYNC;
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status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
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hw->mac.ops.release_swfw_sync(hw, mask);
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return status;
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}
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/**
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* ixgbe_write_phy_reg_x550a - Writes specified PHY register
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* @hw: pointer to hardware structure
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* @reg_addr: 32 bit PHY register to write
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* @device_type: 5 bit device type
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* @phy_data: Data to write to the PHY register
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*
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* Writes a value to specified PHY register using the SWFW lock and PHY Token.
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* The PHY Token is needed since the MDIO is shared between to MAC instances.
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*/
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static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
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u32 device_type, u16 phy_data)
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{
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u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
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s32 status;
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if (hw->mac.ops.acquire_swfw_sync(hw, mask))
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return IXGBE_ERR_SWFW_SYNC;
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status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data);
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hw->mac.ops.release_swfw_sync(hw, mask);
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return status;
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}
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#define X550_COMMON_MAC \
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.init_hw = &ixgbe_init_hw_generic, \
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.start_hw = &ixgbe_start_hw_X540, \
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@ -2673,8 +2724,6 @@ static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
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.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \
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.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \
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.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \
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.read_reg = &ixgbe_read_phy_reg_generic, \
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.write_reg = &ixgbe_write_phy_reg_generic, \
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.setup_link = &ixgbe_setup_phy_link_generic, \
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.set_phy_power = NULL, \
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.check_overtemp = &ixgbe_tn_check_overtemp, \
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@ -2684,12 +2733,16 @@ static const struct ixgbe_phy_operations phy_ops_X550 = {
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X550_COMMON_PHY
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.init = NULL,
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.identify = &ixgbe_identify_phy_generic,
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.read_reg = &ixgbe_read_phy_reg_generic,
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.write_reg = &ixgbe_write_phy_reg_generic,
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};
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static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
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X550_COMMON_PHY
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.init = &ixgbe_init_phy_ops_X550em,
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.identify = &ixgbe_identify_phy_x550em,
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.read_reg = &ixgbe_read_phy_reg_generic,
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.write_reg = &ixgbe_write_phy_reg_generic,
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.read_i2c_combined = &ixgbe_read_i2c_combined_generic,
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.write_i2c_combined = &ixgbe_write_i2c_combined_generic,
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.read_i2c_combined_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
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@ -2697,6 +2750,14 @@ static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
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&ixgbe_write_i2c_combined_generic_unlocked,
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};
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static const struct ixgbe_phy_operations phy_ops_x550em_a = {
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X550_COMMON_PHY
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.init = &ixgbe_init_phy_ops_X550em,
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.identify = &ixgbe_identify_phy_x550em,
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.read_reg = &ixgbe_read_phy_reg_x550a,
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.write_reg = &ixgbe_write_phy_reg_x550a,
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};
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static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
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IXGBE_MVALS_INIT(X550)
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};
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@ -2734,7 +2795,7 @@ const struct ixgbe_info ixgbe_x550em_a_info = {
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.get_invariants = &ixgbe_get_invariants_X550_x,
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.mac_ops = &mac_ops_x550em_a,
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.eeprom_ops = &eeprom_ops_X550EM_x,
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.phy_ops = &phy_ops_X550EM_x,
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.phy_ops = &phy_ops_x550em_a,
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.mbx_ops = &mbx_ops_generic,
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.mvals = ixgbe_mvals_x550em_a,
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};
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