mirror of https://gitee.com/openkylin/linux.git
staging: rtl8732au: Partial clean up of rtl8723a_rf6052.c
Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Jes Sorensen
Greg Kroah-Hartman
parent
7114ca14fc
commit
d3220b7118
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@ -42,21 +42,6 @@
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#include <rtl8723a_hal.h>
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#include <usb_ops_linux.h>
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/*---------------------------Define Local Constant---------------------------*/
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/* Define local structure for debug!!!!! */
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struct rf_shadow_compare_map {
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/* Shadow register value */
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u32 Value;
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/* Compare or not flag */
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u8 Compare;
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/* Record If it had ever modified unpredicted */
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u8 ErrorOrNot;
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/* Recorver Flag */
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u8 Recorver;
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/* */
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u8 Driver_Write;
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};
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/*-----------------------------------------------------------------------------
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* Function: PHY_RF6052SetBandwidth()
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*
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@ -71,20 +56,23 @@ struct rf_shadow_compare_map {
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*
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* Note: For RF type 0222D
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*---------------------------------------------------------------------------*/
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void rtl8723a_phy_rf6052set_bw(
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struct rtw_adapter *Adapter,
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enum ht_channel_width Bandwidth) /* 20M or 40M */
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void rtl8723a_phy_rf6052set_bw(struct rtw_adapter *Adapter,
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enum ht_channel_width Bandwidth) /* 20M or 40M */
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{
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struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
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struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
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switch (Bandwidth) {
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case HT_CHANNEL_WIDTH_20:
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pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400);
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PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
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pHalData->RfRegChnlVal[0] =
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(pHalData->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400;
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PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,
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pHalData->RfRegChnlVal[0]);
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break;
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case HT_CHANNEL_WIDTH_40:
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pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff));
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PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
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pHalData->RfRegChnlVal[0] =
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(pHalData->RfRegChnlVal[0] & 0xfffff3ff);
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PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,
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pHalData->RfRegChnlVal[0]);
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break;
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default:
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break;
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@ -108,7 +96,8 @@ void rtl8723a_phy_rf6052set_bw(
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*
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*---------------------------------------------------------------------------*/
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void rtl823a_phy_rf6052setccktxpower(struct rtw_adapter *Adapter, u8 *pPowerlevel)
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void rtl823a_phy_rf6052setccktxpower(struct rtw_adapter *Adapter,
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u8 *pPowerlevel)
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{
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struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
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struct dm_priv *pdmpriv = &pHalData->dmpriv;
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@ -118,7 +107,8 @@ void rtl823a_phy_rf6052setccktxpower(struct rtw_adapter *Adapter, u8 *pPowerleve
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u8 idx1, idx2;
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u8 *ptr;
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/* According to SD3 eechou's suggestion, we need to disable turbo scan for RU. */
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/* According to SD3 eechou's suggestion, we need to disable
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turbo scan for RU. */
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/* Otherwise, external PA will be broken if power index > 0x20. */
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if (pHalData->EEPROMRegulatory != 0 || pHalData->ExternalPA)
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TurboScanOff = true;
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@ -131,29 +121,37 @@ void rtl823a_phy_rf6052setccktxpower(struct rtw_adapter *Adapter, u8 *pPowerleve
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if (TurboScanOff) {
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for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
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TxAGC[idx1] =
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pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
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(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
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/* 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. */
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TxAGC[idx1] = pPowerlevel[idx1] |
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(pPowerlevel[idx1] << 8) |
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(pPowerlevel[idx1] << 16) |
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(pPowerlevel[idx1] << 24);
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/* 2010/10/18 MH For external PA module.
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We need to limit power index to be less
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than 0x20. */
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if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA)
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TxAGC[idx1] = 0x20;
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}
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}
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} else {
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/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
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/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
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/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
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/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx
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* power. It shall be determined by power training mechanism. */
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/* Currently, we cannot fully disable driver dynamic tx power
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* mechanism because it is referenced by BT coexist mechanism. */
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/* In the future, two mechanism shall be separated from each other
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* and maintained independantly. Thanks for Lanhsin's reminder. */
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if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) {
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TxAGC[RF_PATH_A] = 0x10101010;
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TxAGC[RF_PATH_B] = 0x10101010;
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} else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) {
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} else if (pdmpriv->DynamicTxHighPowerLvl ==
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TxHighPwrLevel_Level2) {
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TxAGC[RF_PATH_A] = 0x00000000;
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TxAGC[RF_PATH_B] = 0x00000000;
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} else {
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for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
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TxAGC[idx1] =
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pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
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(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
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TxAGC[idx1] = pPowerlevel[idx1] |
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(pPowerlevel[idx1] << 8) |
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(pPowerlevel[idx1] << 16) |
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(pPowerlevel[idx1] << 24);
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}
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if (pHalData->EEPROMRegulatory == 0) {
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@ -178,29 +176,24 @@ void rtl823a_phy_rf6052setccktxpower(struct rtw_adapter *Adapter, u8 *pPowerleve
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}
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/* rf-A cck tx power */
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tmpval = TxAGC[RF_PATH_A]&0xff;
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tmpval = TxAGC[RF_PATH_A] & 0xff;
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PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
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tmpval = TxAGC[RF_PATH_A]>>8;
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tmpval = TxAGC[RF_PATH_A] >> 8;
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PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
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/* rf-B cck tx power */
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tmpval = TxAGC[RF_PATH_B]>>24;
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tmpval = TxAGC[RF_PATH_B] >> 24;
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PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
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tmpval = TxAGC[RF_PATH_B]&0x00ffffff;
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tmpval = TxAGC[RF_PATH_B] & 0x00ffffff;
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PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
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} /* PHY_RF6052SetCckTxPower */
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/* powerbase0 for OFDM rates */
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/* powerbase1 for HT MCS rates */
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static void getPowerBase(
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struct rtw_adapter *Adapter,
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u8 *pPowerLevel,
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u8 Channel,
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u32 *OfdmBase,
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u32 *MCSBase
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)
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static void getPowerBase(struct rtw_adapter *Adapter, u8 *pPowerLevel,
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u8 Channel, u32 *OfdmBase, u32 *MCSBase)
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{
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struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
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struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
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u32 powerBase0, powerBase1;
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u8 Legacy_pwrdiff = 0;
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s8 HT20_pwrdiff = 0;
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@ -211,8 +204,9 @@ static void getPowerBase(
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Legacy_pwrdiff = pHalData->TxPwrLegacyHtDiff[i][Channel-1];
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powerBase0 = powerlevel[i] + Legacy_pwrdiff;
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powerBase0 = (powerBase0<<24) | (powerBase0<<16) | (powerBase0<<8) | powerBase0;
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*(OfdmBase+i) = powerBase0;
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powerBase0 = powerBase0 << 24 | powerBase0 << 16 |
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powerBase0 << 8 | powerBase0;
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*(OfdmBase + i) = powerBase0;
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}
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for (i = 0; i < 2; i++) {
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@ -222,36 +216,35 @@ static void getPowerBase(
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powerlevel[i] += HT20_pwrdiff;
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}
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powerBase1 = powerlevel[i];
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powerBase1 = (powerBase1<<24) | (powerBase1<<16) | (powerBase1<<8) | powerBase1;
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*(MCSBase+i) = powerBase1;
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powerBase1 = powerBase1 << 24 | powerBase1 << 16 |
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powerBase1 << 8 | powerBase1;
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*(MCSBase + i) = powerBase1;
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}
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}
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static void getTxPowerWriteValByRegulatory(
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struct rtw_adapter *Adapter,
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u8 Channel,
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u8 index,
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u32 *powerBase0,
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u32 *powerBase1,
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u32 *pOutWriteVal
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)
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static void
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getTxPowerWriteValByRegulatory(struct rtw_adapter *Adapter, u8 Channel,
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u8 index, u32 *powerBase0, u32 *powerBase1,
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u32 *pOutWriteVal)
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{
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struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
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struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
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struct dm_priv *pdmpriv = &pHalData->dmpriv;
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u8 i, chnlGroup = 0, pwr_diff_limit[4];
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u32 writeVal, customer_limit, rf;
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u8 i, chnlGroup = 0, pwr_diff_limit[4];
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u32 writeVal, customer_limit, rf;
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/* Index 0 & 1 = legacy OFDM, 2-5 = HT_MCS rate */
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for (rf = 0; rf < 2; rf++) {
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switch (pHalData->EEPROMRegulatory) {
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case 0: /* Realtek better performance */
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/* increase power diff defined by Realtek for large power */
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/* increase power diff defined by Realtek for
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* large power */
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chnlGroup = 0;
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writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
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((index < 2) ? powerBase0[rf] : powerBase1[rf]);
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break;
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case 1: /* Realtek regulatory */
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/* increase power diff defined by Realtek for regulatory */
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/* increase power diff defined by Realtek for
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* regulatory */
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if (pHalData->pwrGroupCnt == 1)
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chnlGroup = 0;
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if (pHalData->pwrGroupCnt >= 3) {
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@ -262,17 +255,20 @@ static void getTxPowerWriteValByRegulatory(
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else if (Channel > 9)
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chnlGroup = 2;
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if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
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if (pHalData->CurrentChannelBW ==
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HT_CHANNEL_WIDTH_20)
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chnlGroup++;
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else
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chnlGroup += 4;
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}
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writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
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((index < 2) ? powerBase0[rf] : powerBase1[rf]);
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((index < 2) ? powerBase0[rf] :
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powerBase1[rf]);
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break;
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case 2: /* Better regulatory */
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/* don't increase any power diff */
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writeVal = ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
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/* don't increase any power diff */
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writeVal = ((index < 2) ? powerBase0[rf] :
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powerBase1[rf]);
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break;
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case 3: /* Customer defined power diff. */
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chnlGroup = 0;
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@ -299,28 +295,34 @@ static void getTxPowerWriteValByRegulatory(
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break;
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}
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/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
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/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
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/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
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/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power.
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It shall be determined by power training mechanism. */
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/* Currently, we cannot fully disable driver dynamic tx power mechanism
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because it is referenced by BT coexist mechanism. */
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/* In the future, two mechanism shall be separated from each other and
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maintained independantly. Thanks for Lanhsin's reminder. */
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if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
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writeVal = 0x14141414;
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else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
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else if (pdmpriv->DynamicTxHighPowerLvl ==
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TxHighPwrLevel_Level2)
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writeVal = 0x00000000;
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/* 20100628 Joseph: High power mode for BT-Coexist mechanism. */
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/* This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */
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/* 20100628 Joseph: High power mode for BT-Coexist mechanism. */
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/* This mechanism is only applied when
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Driver-Highpower-Mechanism is OFF. */
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if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
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writeVal = writeVal - 0x06060606;
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else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
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writeVal = writeVal;
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*(pOutWriteVal+rf) = writeVal;
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*(pOutWriteVal + rf) = writeVal;
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}
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}
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static void writeOFDMPowerReg(struct rtw_adapter *Adapter, u8 index, u32 *pValue)
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static void writeOFDMPowerReg(struct rtw_adapter *Adapter, u8 index,
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u32 *pValue)
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{
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struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
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struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
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u16 RegOffset_A[6] = {
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rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,
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rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04,
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@ -338,12 +340,13 @@ static void writeOFDMPowerReg(struct rtw_adapter *Adapter, u8 index, u32 *pValue
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for (rf = 0; rf < 2; rf++) {
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writeVal = pValue[rf];
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for (i = 0; i < 4; i++) {
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pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
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if (pwr_val[i] > RF6052_MAX_TX_PWR)
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pwr_val[i] = (u8)((writeVal &
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(0x7f << (i * 8))) >> (i * 8));
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if (pwr_val[i] > RF6052_MAX_TX_PWR)
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pwr_val[i] = RF6052_MAX_TX_PWR;
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}
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writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) |
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(pwr_val[1]<<8) | pwr_val[0];
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writeVal = pwr_val[3] << 24 | pwr_val[2] << 16 |
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pwr_val[1] << 8 | pwr_val[0];
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if (rf == 0)
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RegOffset = RegOffset_A[index];
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@ -352,7 +355,8 @@ static void writeOFDMPowerReg(struct rtw_adapter *Adapter, u8 index, u32 *pValue
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PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal);
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/* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */
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/* 201005115 Joseph: Set Tx Power diff for Tx power
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training mechanism. */
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if (((pHalData->rf_type == RF_2T2R) &&
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(RegOffset == rTxAGC_A_Mcs15_Mcs12 ||
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RegOffset == rTxAGC_B_Mcs15_Mcs12)) ||
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@ -360,15 +364,19 @@ static void writeOFDMPowerReg(struct rtw_adapter *Adapter, u8 index, u32 *pValue
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(RegOffset == rTxAGC_A_Mcs07_Mcs04 ||
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RegOffset == rTxAGC_B_Mcs07_Mcs04))) {
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writeVal = pwr_val[3];
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if (RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04)
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if (RegOffset == rTxAGC_A_Mcs15_Mcs12 ||
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RegOffset == rTxAGC_A_Mcs07_Mcs04)
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RegOffset = 0xc90;
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if (RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04)
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if (RegOffset == rTxAGC_B_Mcs15_Mcs12 ||
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RegOffset == rTxAGC_B_Mcs07_Mcs04)
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RegOffset = 0xc98;
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for (i = 0; i < 3; i++) {
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if (i != 2)
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writeVal = (writeVal > 8) ? (writeVal-8) : 0;
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writeVal = (writeVal > 8) ?
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(writeVal - 8) : 0;
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else
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writeVal = (writeVal > 6) ? (writeVal-6) : 0;
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writeVal = (writeVal > 6) ?
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(writeVal - 6) : 0;
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rtl8723au_write8(Adapter, RegOffset + i,
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(u8)writeVal);
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}
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@ -379,8 +387,9 @@ static void writeOFDMPowerReg(struct rtw_adapter *Adapter, u8 index, u32 *pValue
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* Function: PHY_RF6052SetOFDMTxPower
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*
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* Overview: For legacy and HY OFDM, we must read EEPROM TX power index for
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* different channel and read original value in TX power register area from
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* 0xe00. We increase offset and original value to be correct tx pwr.
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* different channel and read original value in TX power
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* register area from 0xe00. We increase offset and
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* original value to be correct tx pwr.
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*
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* Input: NONE
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*
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@ -389,20 +398,23 @@ static void writeOFDMPowerReg(struct rtw_adapter *Adapter, u8 index, u32 *pValue
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* Return: NONE
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*
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* Revised History:
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* When Who Remark
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* 11/05/2008 MHC Simulate 8192 series method.
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* 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to
|
||||
* A/B pwr difference or legacy/HT pwr diff.
|
||||
* 2. We concern with path B legacy/HT OFDM difference.
|
||||
* 01/22/2009 MHC Support new EPRO format from SD3.
|
||||
* When Remark
|
||||
* 11/05/2008 MHC Simulate 8192 series method.
|
||||
* 01/06/2009 MHC 1. Prevent Path B tx power overflow or
|
||||
* underflow dure to A/B pwr difference or
|
||||
* legacy/HT pwr diff.
|
||||
* 2. We concern with path B legacy/HT OFDM difference.
|
||||
* 01/22/2009 MHC Support new EPRO format from SD3.
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
void rtl8723a_PHY_RF6052SetOFDMTxPower(struct rtw_adapter *Adapter, u8 *pPowerLevel, u8 Channel)
|
||||
void rtl8723a_PHY_RF6052SetOFDMTxPower(struct rtw_adapter *Adapter,
|
||||
u8 *pPowerLevel, u8 Channel)
|
||||
{
|
||||
u32 writeVal[2], powerBase0[2], powerBase1[2];
|
||||
u8 index = 0;
|
||||
|
||||
getPowerBase(Adapter, pPowerLevel, Channel, &powerBase0[0], &powerBase1[0]);
|
||||
getPowerBase(Adapter, pPowerLevel, Channel,
|
||||
&powerBase0[0], &powerBase1[0]);
|
||||
|
||||
for (index = 0; index < 6; index++) {
|
||||
getTxPowerWriteValByRegulatory(Adapter, Channel, index,
|
||||
|
|
@ -416,7 +428,7 @@ static int phy_RF6052_Config_ParaFile(struct rtw_adapter *Adapter)
|
|||
{
|
||||
u32 u4RegValue = 0;
|
||||
u8 eRFPath;
|
||||
struct bb_reg_define *pPhyReg;
|
||||
struct bb_reg_define *pPhyReg;
|
||||
int rtStatus = _SUCCESS;
|
||||
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
|
||||
|
||||
|
|
@ -430,15 +442,17 @@ static int phy_RF6052_Config_ParaFile(struct rtw_adapter *Adapter)
|
|||
/*----Store original RFENV control type----*/
|
||||
switch (eRFPath) {
|
||||
case RF_PATH_A:
|
||||
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
|
||||
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs,
|
||||
bRFSI_RFENV);
|
||||
break;
|
||||
case RF_PATH_B:
|
||||
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
|
||||
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs,
|
||||
bRFSI_RFENV << 16);
|
||||
break;
|
||||
}
|
||||
|
||||
/*----Set RF_ENV enable----*/
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1);
|
||||
udelay(1);/* PlatformStallExecution(1); */
|
||||
|
||||
/*----Set RF_ENV output high----*/
|
||||
|
|
@ -446,10 +460,12 @@ static int phy_RF6052_Config_ParaFile(struct rtw_adapter *Adapter)
|
|||
udelay(1);/* PlatformStallExecution(1); */
|
||||
|
||||
/* Set bit number of Address and Data for RF register */
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength,
|
||||
0x0); /* Set 1 to 4 bits for 8255 */
|
||||
udelay(1);/* PlatformStallExecution(1); */
|
||||
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength,
|
||||
0x0); /* Set 0 to 12 bits for 8255 */
|
||||
udelay(1);/* PlatformStallExecution(1); */
|
||||
|
||||
/*----Initialize RF fom connfiguration file----*/
|
||||
|
|
@ -464,15 +480,16 @@ static int phy_RF6052_Config_ParaFile(struct rtw_adapter *Adapter)
|
|||
/*----Restore RFENV control type----*/;
|
||||
switch (eRFPath) {
|
||||
case RF_PATH_A:
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfintfs,
|
||||
bRFSI_RFENV, u4RegValue);
|
||||
break;
|
||||
case RF_PATH_B:
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfintfs,
|
||||
bRFSI_RFENV << 16, u4RegValue);
|
||||
break;
|
||||
}
|
||||
|
||||
if (rtStatus != _SUCCESS) {
|
||||
/* RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); */
|
||||
goto phy_RF6052_Config_ParaFile_Fail;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue