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PCI: Allow PCIe Capability link-related register access for switches
Every PCIe device has a link, except Root Complex Integrated Endpoints and Root Complex Event Collectors. Previously we didn't give access to PCIe capability link-related registers for Upstream Ports, Downstream Ports, and Bridges, so attempts to read PCI_EXP_LNKCTL incorrectly returned zero. See PCIe spec r3.0, sec 7.8 and 1.3.2.3. Reference: http://lkml.kernel.org/r/979A8436335E3744ADCD3A9F2A2B68A52AD136BE@SJEXCHMB10.corp.ad.broadcom.com Reported-by: Yuval Mintz <yuvalmin@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-By: Jiang Liu <jiang.liu@huawei.com>
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@ -485,9 +485,13 @@ static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
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int type = pci_pcie_type(dev);
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return pcie_cap_version(dev) > 1 ||
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type == PCI_EXP_TYPE_ROOT_PORT ||
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type == PCI_EXP_TYPE_ENDPOINT ||
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type == PCI_EXP_TYPE_LEG_END;
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type == PCI_EXP_TYPE_LEG_END ||
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type == PCI_EXP_TYPE_ROOT_PORT ||
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type == PCI_EXP_TYPE_UPSTREAM ||
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type == PCI_EXP_TYPE_DOWNSTREAM ||
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type == PCI_EXP_TYPE_PCI_BRIDGE ||
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type == PCI_EXP_TYPE_PCIE_BRIDGE;
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}
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static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
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