mirror of https://gitee.com/openkylin/linux.git
Renesas ARM Based SoC r8a73a4 CCF and Multiplatform Updates for v4.1
* Add CCF and them multiplatform support to r8a73a4 SoC and its
ape6evm board.
* Then remove legacy r8a73a4 SoC and ape6evm board code.
----------------------------------------------------------------
Geert Uytterhoeven (6):
ARM: shmobile: r8a73a4 dtsi: Add Bus State Controller node
ARM: shmobile: ape6evm dts: Move Ethernet node to BSC
ARM: shmobile: r8a73a4: Move pfc node to work around probe ordering bug
ARM: shmobile: ape6evm dts: Drop console= bootargs parameter
PM / Domains: R-Mobile SYSC: Document R-Mobile APE6 (r8a73a4) binding
ARM: shmobile: r8a73a4 dtsi: Add PM domain support
Laurent Pinchart (1):
ARM: shmobile: r8a73a4: Remove legacy code
Simon Horman (1):
ARM: shmobile: r8a73a4: ape6evm: Remove legacy platform
Ulrich Hecht (5):
ARM: shmobile: r8a73a4: Add CPG register bits header
ARM: shmobile: r8a73a4: Common clock framework DT description
ARM: shmobile: ape6evm: Disable legacy clock initialization
ARM: shmobile: r8a73a4: Add MSTP clock assignments to DT
ARM: shmobile: ape6evm-reference: Remove board C code and DT file
Documentation/devicetree/bindings/arm/shmobile.txt | 2 -
.../bindings/power/renesas,sysc-rmobile.txt | 1 +
MAINTAINERS | 1 -
arch/arm/boot/dts/Makefile | 2 -
arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 156 -----
arch/arm/boot/dts/r8a73a4-ape6evm.dts | 37 +-
arch/arm/boot/dts/r8a73a4.dtsi | 557 ++++++++++++++++-
arch/arm/configs/ape6evm_defconfig | 109 ----
arch/arm/mach-shmobile/Kconfig | 25 -
arch/arm/mach-shmobile/Makefile | 3 -
arch/arm/mach-shmobile/Makefile.boot | 2 -
arch/arm/mach-shmobile/board-ape6evm-reference.c | 60 --
arch/arm/mach-shmobile/board-ape6evm.c | 306 ----------
arch/arm/mach-shmobile/clock-r8a73a4.c | 659 ---------------------
arch/arm/mach-shmobile/r8a73a4.h | 17 -
arch/arm/mach-shmobile/setup-r8a73a4.c | 273 +--------
include/dt-bindings/clock/r8a73a4-clock.h | 62 ++
17 files changed, 615 insertions(+), 1657 deletions(-)
delete mode 100644 arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
delete mode 100644 arch/arm/configs/ape6evm_defconfig
delete mode 100644 arch/arm/mach-shmobile/board-ape6evm-reference.c
delete mode 100644 arch/arm/mach-shmobile/board-ape6evm.c
delete mode 100644 arch/arm/mach-shmobile/clock-r8a73a4.c
delete mode 100644 arch/arm/mach-shmobile/r8a73a4.h
create mode 100644 include/dt-bindings/clock/r8a73a4-clock.h
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Merge tag 'renesas-r8a73a4-ccf-and-multiplatform-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/multiplatform
Merge "Renesas ARM Based SoC r8a73a4 CCF and Multiplatform Updates for
v4.1" from Simon Horman:
* Add CCF and them multiplatform support to r8a73a4 SoC and its
ape6evm board.
* Then remove legacy r8a73a4 SoC and ape6evm board code.
----------------------------------------------------------------
Geert Uytterhoeven (6):
ARM: shmobile: r8a73a4 dtsi: Add Bus State Controller node
ARM: shmobile: ape6evm dts: Move Ethernet node to BSC
ARM: shmobile: r8a73a4: Move pfc node to work around probe ordering bug
ARM: shmobile: ape6evm dts: Drop console= bootargs parameter
PM / Domains: R-Mobile SYSC: Document R-Mobile APE6 (r8a73a4) binding
ARM: shmobile: r8a73a4 dtsi: Add PM domain support
Laurent Pinchart (1):
ARM: shmobile: r8a73a4: Remove legacy code
Simon Horman (1):
ARM: shmobile: r8a73a4: ape6evm: Remove legacy platform
Ulrich Hecht (5):
ARM: shmobile: r8a73a4: Add CPG register bits header
ARM: shmobile: r8a73a4: Common clock framework DT description
ARM: shmobile: ape6evm: Disable legacy clock initialization
ARM: shmobile: r8a73a4: Add MSTP clock assignments to DT
ARM: shmobile: ape6evm-reference: Remove board C code and DT file
Documentation/devicetree/bindings/arm/shmobile.txt | 2 -
.../bindings/power/renesas,sysc-rmobile.txt | 1 +
MAINTAINERS | 1 -
arch/arm/boot/dts/Makefile | 2 -
arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 156 -----
arch/arm/boot/dts/r8a73a4-ape6evm.dts | 37 +-
arch/arm/boot/dts/r8a73a4.dtsi | 557 ++++++++++++++++-
arch/arm/configs/ape6evm_defconfig | 109 ----
arch/arm/mach-shmobile/Kconfig | 25 -
arch/arm/mach-shmobile/Makefile | 3 -
arch/arm/mach-shmobile/Makefile.boot | 2 -
arch/arm/mach-shmobile/board-ape6evm-reference.c | 60 --
arch/arm/mach-shmobile/board-ape6evm.c | 306 ----------
arch/arm/mach-shmobile/clock-r8a73a4.c | 659 ---------------------
arch/arm/mach-shmobile/r8a73a4.h | 17 -
arch/arm/mach-shmobile/setup-r8a73a4.c | 273 +--------
include/dt-bindings/clock/r8a73a4-clock.h | 62 ++
17 files changed, 615 insertions(+), 1657 deletions(-)
delete mode 100644 arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
delete mode 100644 arch/arm/configs/ape6evm_defconfig
delete mode 100644 arch/arm/mach-shmobile/board-ape6evm-reference.c
delete mode 100644 arch/arm/mach-shmobile/board-ape6evm.c
delete mode 100644 arch/arm/mach-shmobile/clock-r8a73a4.c
delete mode 100644 arch/arm/mach-shmobile/r8a73a4.h
create mode 100644 include/dt-bindings/clock/r8a73a4-clock.h
* tag 'renesas-r8a73a4-ccf-and-multiplatform-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a73a4: Remove legacy code
ARM: shmobile: r8a73a4 dtsi: Add PM domain support
PM / Domains: R-Mobile SYSC: Document R-Mobile APE6 (r8a73a4) binding
ARM: shmobile: ape6evm dts: Drop console= bootargs parameter
ARM: shmobile: r8a73a4: ape6evm: Remove legacy platform
ARM: shmobile: ape6evm-reference: Remove board C code and DT file
ARM: shmobile: r8a73a4: Move pfc node to work around probe ordering bug
ARM: shmobile: ape6evm dts: Move Ethernet node to BSC
ARM: shmobile: r8a73a4 dtsi: Add Bus State Controller node
ARM: shmobile: r8a73a4: Add MSTP clock assignments to DT
ARM: shmobile: ape6evm: Disable legacy clock initialization
ARM: shmobile: r8a73a4: Common clock framework DT description
ARM: shmobile: r8a73a4: Add CPG register bits header
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
d36d520ae6
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@ -35,8 +35,6 @@ Boards:
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compatible = "renesas,alt", "renesas,r8a7794"
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- APE6-EVM
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compatible = "renesas,ape6evm", "renesas,r8a73a4"
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- APE6-EVM - Reference Device Tree Implementation
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compatible = "renesas,ape6evm-reference", "renesas,r8a73a4"
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- Atmark Techno Armadillo-800 EVA
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compatible = "renesas,armadillo800eva"
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- BOCK-W
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|
|
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@ -11,6 +11,7 @@ Required properties:
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- compatible: Should be "renesas,sysc-<soctype>", "renesas,sysc-rmobile" as
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fallback.
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Examples with soctypes are:
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- "renesas,sysc-r8a73a4" (R-Mobile APE6)
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- "renesas,sysc-r8a7740" (R-Mobile A1)
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- "renesas,sysc-sh73a0" (SH-Mobile AG5)
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- reg: Two address start and address range blocks for the device:
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|
|
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@ -1414,7 +1414,6 @@ F: arch/arm/boot/dts/emev2*
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F: arch/arm/boot/dts/r7s*
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F: arch/arm/boot/dts/r8a*
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F: arch/arm/boot/dts/sh*
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F: arch/arm/configs/ape6evm_defconfig
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F: arch/arm/configs/armadillo800eva_defconfig
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F: arch/arm/configs/bockw_defconfig
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F: arch/arm/configs/kzm9g_defconfig
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|
|
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@ -464,8 +464,6 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
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s5pv210-smdkv210.dtb \
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s5pv210-torbreck.dtb
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dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
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r8a73a4-ape6evm.dtb \
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r8a73a4-ape6evm-reference.dtb \
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r8a7740-armadillo800eva.dtb \
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r8a7778-bockw.dtb \
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r8a7778-bockw-reference.dtb \
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|
|
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@ -1,156 +0,0 @@
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/*
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* Device Tree Source for the APE6EVM board
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/dts-v1/;
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#include "r8a73a4.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "APE6EVM";
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compatible = "renesas,ape6evm-reference", "renesas,r8a73a4";
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aliases {
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serial0 = &scifa0;
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};
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chosen {
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bootargs = "ignore_loglevel rw";
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stdout-path = &scifa0;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x40000000>;
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};
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memory@200000000 {
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device_type = "memory";
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reg = <2 0x00000000 0 0x40000000>;
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};
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vcc_mmc0: regulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "MMC0 Vcc";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-always-on;
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};
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vcc_sdhi0: regulator@1 {
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compatible = "regulator-fixed";
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regulator-name = "SDHI0 Vcc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&pfc 76 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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/* Common 3.3V rail, used by several devices on APE6EVM */
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ape6evm_fixed_3v3: regulator@2 {
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compatible = "regulator-fixed";
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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lbsc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0x20000000>;
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};
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};
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&i2c5 {
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status = "okay";
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vdd_dvfs: max8973@1b {
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compatible = "maxim,max8973";
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reg = <0x1b>;
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regulator-min-microvolt = <935000>;
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regulator-max-microvolt = <1200000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&cpu0 {
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cpu0-supply = <&vdd_dvfs>;
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operating-points = <
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/* kHz uV */
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1950000 1115000
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1462500 995000
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>;
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voltage-tolerance = <1>; /* 1% */
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};
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&cmt1 {
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status = "okay";
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};
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&pfc {
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scifa0_pins: serial0 {
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renesas,groups = "scifa0_data";
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renesas,function = "scifa0";
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};
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mmc0_pins: mmc {
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renesas,groups = "mmc0_data8", "mmc0_ctrl";
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renesas,function = "mmc0";
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};
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sdhi0_pins: sd0 {
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renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
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renesas,function = "sdhi0";
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};
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sdhi1_pins: sd1 {
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renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
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renesas,function = "sdhi1";
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};
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};
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&mmcif0 {
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vmmc-supply = <&vcc_mmc0>;
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bus-width = <8>;
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non-removable;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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status = "okay";
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};
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&scifa0 {
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pinctrl-0 = <&scifa0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&sdhi0 {
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vmmc-supply = <&vcc_sdhi0>;
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bus-width = <4>;
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toshiba,mmc-wrprotect-disable;
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pinctrl-names = "default";
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pinctrl-0 = <&sdhi0_pins>;
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status = "okay";
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};
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&sdhi1 {
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vmmc-supply = <&ape6evm_fixed_3v3>;
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bus-width = <4>;
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broken-cd;
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toshiba,mmc-wrprotect-disable;
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pinctrl-names = "default";
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pinctrl-0 = <&sdhi1_pins>;
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status = "okay";
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};
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@ -22,7 +22,7 @@ aliases {
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|||
};
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chosen {
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bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
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bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp rw";
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stdout-path = &scifa0;
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};
|
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|
||||
|
|
@ -72,26 +72,6 @@ ape6evm_fixed_3v3: regulator@3 {
|
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regulator-always-on;
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};
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lbsc {
|
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0x20000000>;
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ethernet@8000000 {
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compatible = "smsc,lan9220", "smsc,lan9115";
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reg = <0x08000000 0x1000>;
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interrupt-parent = <&irqc1>;
|
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interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
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phy-mode = "mii";
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reg-io-width = <4>;
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smsc,irq-active-high;
|
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smsc,irq-push-pull;
|
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vdd33a-supply = <&ape6evm_fixed_3v3>;
|
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vddvario-supply = <&ape6evm_fixed_1v8>;
|
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};
|
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};
|
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|
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leds {
|
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compatible = "gpio-leds";
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led1 {
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|
|
@ -184,6 +164,21 @@ &cpu0 {
|
|||
voltage-tolerance = <1>; /* 1% */
|
||||
};
|
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|
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&bsc {
|
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ethernet@8000000 {
|
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compatible = "smsc,lan9220", "smsc,lan9115";
|
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reg = <0x08000000 0x1000>;
|
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interrupt-parent = <&irqc1>;
|
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interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
|
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phy-mode = "mii";
|
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reg-io-width = <4>;
|
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smsc,irq-active-high;
|
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smsc,irq-push-pull;
|
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vdd33a-supply = <&ape6evm_fixed_3v3>;
|
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vddvario-supply = <&ape6evm_fixed_1v8>;
|
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};
|
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};
|
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&cmt1 {
|
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status = "okay";
|
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};
|
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|
|
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|
|
@ -9,6 +9,7 @@
|
|||
* kind, whether express or implied.
|
||||
*/
|
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#include <dt-bindings/clock/r8a73a4-clock.h>
|
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#include <dt-bindings/interrupt-controller/arm-gic.h>
|
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#include <dt-bindings/interrupt-controller/irq.h>
|
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|
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|
|
@ -27,9 +28,15 @@ cpu0: cpu@0 {
|
|||
compatible = "arm,cortex-a15";
|
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reg = <0>;
|
||||
clock-frequency = <1500000000>;
|
||||
power-domains = <&pd_a2sl>;
|
||||
};
|
||||
};
|
||||
|
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ptm {
|
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compatible = "arm,coresight-etm3x";
|
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power-domains = <&pd_d4>;
|
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};
|
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|
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timer {
|
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compatible = "arm,armv7-timer";
|
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interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
|
|
@ -41,11 +48,13 @@ timer {
|
|||
dbsc1: memory-controller@e6790000 {
|
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compatible = "renesas,dbsc-r8a73a4";
|
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reg = <0 0xe6790000 0 0x10000>;
|
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power-domains = <&pd_a3bc>;
|
||||
};
|
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|
||||
dbsc2: memory-controller@e67a0000 {
|
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compatible = "renesas,dbsc-r8a73a4";
|
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reg = <0 0xe67a0000 0 0x10000>;
|
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power-domains = <&pd_a3bc>;
|
||||
};
|
||||
|
||||
dmac: dma-multiplexer {
|
||||
|
|
@ -87,38 +96,19 @@ dma0: dma-controller@e6700020 {
|
|||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15",
|
||||
"ch16", "ch17", "ch18", "ch19";
|
||||
clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
|
||||
power-domains = <&pd_a3sp>;
|
||||
};
|
||||
};
|
||||
|
||||
pfc: pfc@e6050000 {
|
||||
compatible = "renesas,pfc-r8a73a4";
|
||||
reg = <0 0xe6050000 0 0x9000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts-extended =
|
||||
<&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
|
||||
<&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
|
||||
<&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
|
||||
<&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
|
||||
<&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
|
||||
<&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
|
||||
<&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
|
||||
<&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
|
||||
<&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
|
||||
<&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
|
||||
<&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
|
||||
<&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
|
||||
<&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
|
||||
<&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
|
||||
<&irqc1 24 0>, <&irqc1 25 0>;
|
||||
};
|
||||
|
||||
i2c5: i2c@e60b0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
|
||||
reg = <0 0xe60b0000 0 0x428>;
|
||||
interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
|
||||
power-domains = <&pd_a3sp>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -127,6 +117,9 @@ cmt1: timer@e6130000 {
|
|||
compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
|
||||
reg = <0 0xe6130000 0 0x1004>;
|
||||
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&pd_c5>;
|
||||
|
||||
renesas,channels-mask = <0xff>;
|
||||
|
||||
|
|
@ -170,6 +163,7 @@ irqc0: interrupt-controller@e61c0000 {
|
|||
<0 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 30 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&pd_c4>;
|
||||
};
|
||||
|
||||
irqc1: interrupt-controller@e61c0200 {
|
||||
|
|
@ -203,6 +197,31 @@ irqc1: interrupt-controller@e61c0200 {
|
|||
<0 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 56 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&pd_c4>;
|
||||
};
|
||||
|
||||
pfc: pfc@e6050000 {
|
||||
compatible = "renesas,pfc-r8a73a4";
|
||||
reg = <0 0xe6050000 0 0x9000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts-extended =
|
||||
<&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
|
||||
<&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
|
||||
<&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
|
||||
<&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
|
||||
<&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
|
||||
<&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
|
||||
<&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
|
||||
<&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
|
||||
<&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
|
||||
<&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
|
||||
<&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
|
||||
<&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
|
||||
<&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
|
||||
<&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
|
||||
<&irqc1 24 0>, <&irqc1 25 0>;
|
||||
power-domains = <&pd_c5>;
|
||||
};
|
||||
|
||||
thermal@e61f0000 {
|
||||
|
|
@ -210,6 +229,8 @@ thermal@e61f0000 {
|
|||
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
|
||||
<0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
|
||||
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
|
||||
power-domains = <&pd_c5>;
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
|
|
@ -218,6 +239,8 @@ i2c0: i2c@e6500000 {
|
|||
compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
|
||||
reg = <0 0xe6500000 0 0x428>;
|
||||
interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
|
||||
power-domains = <&pd_a3sp>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -227,6 +250,8 @@ i2c1: i2c@e6510000 {
|
|||
compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
|
||||
reg = <0 0xe6510000 0 0x428>;
|
||||
interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
|
||||
power-domains = <&pd_a3sp>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -236,6 +261,8 @@ i2c2: i2c@e6520000 {
|
|||
compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
|
||||
reg = <0 0xe6520000 0 0x428>;
|
||||
interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
|
||||
power-domains = <&pd_a3sp>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -245,6 +272,8 @@ i2c3: i2c@e6530000 {
|
|||
compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
|
||||
reg = <0 0xe6530000 0 0x428>;
|
||||
interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
|
||||
power-domains = <&pd_a3sp>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -254,6 +283,8 @@ i2c4: i2c@e6540000 {
|
|||
compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
|
||||
reg = <0 0xe6540000 0 0x428>;
|
||||
interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
|
||||
power-domains = <&pd_a3sp>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -263,6 +294,8 @@ i2c6: i2c@e6550000 {
|
|||
compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
|
||||
reg = <0 0xe6550000 0 0x428>;
|
||||
interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
|
||||
power-domains = <&pd_a3sp>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -272,6 +305,8 @@ i2c7: i2c@e6560000 {
|
|||
compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
|
||||
reg = <0 0xe6560000 0 0x428>;
|
||||
interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
|
||||
power-domains = <&pd_a3sp>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -281,6 +316,8 @@ i2c8: i2c@e6570000 {
|
|||
compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
|
||||
reg = <0 0xe6570000 0 0x428>;
|
||||
interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
|
||||
power-domains = <&pd_a3sp>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -288,6 +325,9 @@ scifb0: serial@e6c20000 {
|
|||
compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
|
||||
reg = <0 0xe6c20000 0 0x100>;
|
||||
interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&pd_a3sp>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -295,6 +335,9 @@ scifb1: serial@e6c30000 {
|
|||
compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
|
||||
reg = <0 0xe6c30000 0 0x100>;
|
||||
interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&pd_a3sp>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -302,6 +345,9 @@ scifa0: serial@e6c40000 {
|
|||
compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
|
||||
reg = <0 0xe6c40000 0 0x100>;
|
||||
interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&pd_a3sp>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -309,6 +355,9 @@ scifa1: serial@e6c50000 {
|
|||
compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
|
||||
reg = <0 0xe6c50000 0 0x100>;
|
||||
interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&pd_a3sp>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -316,6 +365,9 @@ scifb2: serial@e6ce0000 {
|
|||
compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
|
||||
reg = <0 0xe6ce0000 0 0x100>;
|
||||
interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&pd_a3sp>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -323,6 +375,9 @@ scifb3: serial@e6cf0000 {
|
|||
compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
|
||||
reg = <0 0xe6cf0000 0 0x100>;
|
||||
interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
|
||||
clock-names = "sci_ick";
|
||||
power-domains = <&pd_c4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -330,6 +385,8 @@ sdhi0: sd@ee100000 {
|
|||
compatible = "renesas,sdhi-r8a73a4";
|
||||
reg = <0 0xee100000 0 0x100>;
|
||||
interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
|
||||
power-domains = <&pd_a3sp>;
|
||||
cap-sd-highspeed;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -338,6 +395,8 @@ sdhi1: sd@ee120000 {
|
|||
compatible = "renesas,sdhi-r8a73a4";
|
||||
reg = <0 0xee120000 0 0x100>;
|
||||
interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
|
||||
power-domains = <&pd_a3sp>;
|
||||
cap-sd-highspeed;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -346,6 +405,8 @@ sdhi2: sd@ee140000 {
|
|||
compatible = "renesas,sdhi-r8a73a4";
|
||||
reg = <0 0xee140000 0 0x100>;
|
||||
interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
|
||||
power-domains = <&pd_a3sp>;
|
||||
cap-sd-highspeed;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -354,6 +415,8 @@ mmcif0: mmc@ee200000 {
|
|||
compatible = "renesas,sh-mmcif";
|
||||
reg = <0 0xee200000 0 0x80>;
|
||||
interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
|
||||
power-domains = <&pd_a3sp>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -362,6 +425,8 @@ mmcif1: mmc@ee220000 {
|
|||
compatible = "renesas,sh-mmcif";
|
||||
reg = <0 0xee220000 0 0x80>;
|
||||
interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
|
||||
power-domains = <&pd_a3sp>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -377,4 +442,450 @@ gic: interrupt-controller@f1001000 {
|
|||
<0 0xf1006000 0 0x2000>;
|
||||
interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
bsc: bus@fec10000 {
|
||||
compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
|
||||
"simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0x20000000>;
|
||||
reg = <0 0xfec10000 0 0x400>;
|
||||
clocks = <&zb_clk>;
|
||||
power-domains = <&pd_c4>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* External root clocks */
|
||||
extalr_clk: extalr_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "extalr";
|
||||
};
|
||||
extal1_clk: extal1_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "extal1";
|
||||
};
|
||||
extal2_clk: extal2_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
clock-output-names = "extal2";
|
||||
};
|
||||
fsiack_clk: fsiack_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "fsiack";
|
||||
};
|
||||
fsibck_clk: fsibck_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "fsibck";
|
||||
};
|
||||
|
||||
/* Special CPG clocks */
|
||||
cpg_clocks: cpg_clocks@e6150000 {
|
||||
compatible = "renesas,r8a73a4-cpg-clocks";
|
||||
reg = <0 0xe6150000 0 0x10000>;
|
||||
clocks = <&extal1_clk>, <&extal2_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "main", "pll0", "pll1", "pll2",
|
||||
"pll2s", "pll2h", "z", "z2",
|
||||
"i", "m3", "b", "m1", "m2",
|
||||
"zx", "zs", "hp";
|
||||
};
|
||||
|
||||
/* Variable factor clocks (DIV6) */
|
||||
zb_clk: zb_clk@e6150010 {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150010 0 4>;
|
||||
clocks = <&pll1_div2_clk>, <0>,
|
||||
<&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "zb";
|
||||
};
|
||||
sdhi0_clk: sdhi0_clk@e6150074 {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150074 0 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
|
||||
<0>, <&extal2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sdhi0ck";
|
||||
};
|
||||
sdhi1_clk: sdhi1_clk@e6150078 {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150078 0 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
|
||||
<0>, <&extal2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sdhi1ck";
|
||||
};
|
||||
sdhi2_clk: sdhi2_clk@e615007c {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe615007c 0 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
|
||||
<0>, <&extal2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sdhi2ck";
|
||||
};
|
||||
mmc0_clk: mmc0_clk@e6150240 {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150240 0 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
|
||||
<0>, <&extal2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mmc0";
|
||||
};
|
||||
mmc1_clk: mmc1_clk@e6150244 {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150244 0 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
|
||||
<0>, <&extal2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mmc1";
|
||||
};
|
||||
vclk1_clk: vclk1_clk@e6150008 {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150008 0 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
|
||||
<0>, <&extal2_clk>, <&main_div2_clk>,
|
||||
<&extalr_clk>, <0>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "vclk1";
|
||||
};
|
||||
vclk2_clk: vclk2_clk@e615000c {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe615000c 0 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
|
||||
<0>, <&extal2_clk>, <&main_div2_clk>,
|
||||
<&extalr_clk>, <0>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "vclk2";
|
||||
};
|
||||
vclk3_clk: vclk3_clk@e615001c {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe615001c 0 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
|
||||
<0>, <&extal2_clk>, <&main_div2_clk>,
|
||||
<&extalr_clk>, <0>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "vclk3";
|
||||
};
|
||||
vclk4_clk: vclk4_clk@e6150014 {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150014 0 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
|
||||
<0>, <&extal2_clk>, <&main_div2_clk>,
|
||||
<&extalr_clk>, <0>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "vclk4";
|
||||
};
|
||||
vclk5_clk: vclk5_clk@e6150034 {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150034 0 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
|
||||
<0>, <&extal2_clk>, <&main_div2_clk>,
|
||||
<&extalr_clk>, <0>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "vclk5";
|
||||
};
|
||||
fsia_clk: fsia_clk@e6150018 {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150018 0 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
|
||||
<&fsiack_clk>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "fsia";
|
||||
};
|
||||
fsib_clk: fsib_clk@e6150090 {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150090 0 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
|
||||
<&fsibck_clk>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "fsib";
|
||||
};
|
||||
mp_clk: mp_clk@e6150080 {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150080 0 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
|
||||
<&extal2_clk>, <&extal2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mp";
|
||||
};
|
||||
m4_clk: m4_clk@e6150098 {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150098 0 4>;
|
||||
clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "m4";
|
||||
};
|
||||
hsi_clk: hsi_clk@e615026c {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe615026c 0 4>;
|
||||
clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
|
||||
<&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "hsi";
|
||||
};
|
||||
spuv_clk: spuv_clk@e6150094 {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe6150094 0 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
|
||||
<&extal2_clk>, <&extal2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "spuv";
|
||||
};
|
||||
|
||||
/* Fixed factor clocks */
|
||||
main_div2_clk: main_div2_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "main_div2";
|
||||
};
|
||||
pll0_div2_clk: pll0_div2_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "pll0_div2";
|
||||
};
|
||||
pll1_div2_clk: pll1_div2_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "pll1_div2";
|
||||
};
|
||||
extal1_div2_clk: extal1_div2_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&extal1_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "extal1_div2";
|
||||
};
|
||||
|
||||
/* Gate clocks */
|
||||
mstp2_clks: mstp2_clks@e6150138 {
|
||||
compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
|
||||
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
|
||||
<&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
|
||||
R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
|
||||
R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
|
||||
R8A73A4_CLK_DMAC
|
||||
>;
|
||||
clock-output-names =
|
||||
"scifa0", "scifa1", "scifb0", "scifb1",
|
||||
"scifb2", "scifb3", "dmac";
|
||||
};
|
||||
mstp3_clks: mstp3_clks@e615013c {
|
||||
compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
|
||||
clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
|
||||
<&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
|
||||
<&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
|
||||
<&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
|
||||
R8A73A4_CLK_HP>, <&cpg_clocks
|
||||
R8A73A4_CLK_HP>, <&extalr_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
|
||||
R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
|
||||
R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
|
||||
R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
|
||||
R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
|
||||
R8A73A4_CLK_CMT1
|
||||
>;
|
||||
clock-output-names =
|
||||
"iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
|
||||
"mmcif0", "iic6", "iic7", "iic0", "iic1",
|
||||
"cmt1";
|
||||
};
|
||||
mstp4_clks: mstp4_clks@e6150140 {
|
||||
compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
|
||||
clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
|
||||
<&cpg_clocks R8A73A4_CLK_HP>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
|
||||
R8A73A4_CLK_IIC3
|
||||
>;
|
||||
clock-output-names =
|
||||
"iic5", "iic4", "iic3";
|
||||
};
|
||||
mstp5_clks: mstp5_clks@e6150144 {
|
||||
compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
|
||||
clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
|
||||
>;
|
||||
clock-output-names =
|
||||
"thermal", "iic8";
|
||||
};
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
|
||||
reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
|
||||
|
||||
pm-domains {
|
||||
pd_c5: c5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#power-domain-cells = <0>;
|
||||
|
||||
pd_c4: c4@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#power-domain-cells = <0>;
|
||||
|
||||
pd_a3sg: a3sg@16 {
|
||||
reg = <16>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_a3ex: a3ex@17 {
|
||||
reg = <17>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_a3sp: a3sp@18 {
|
||||
reg = <18>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#power-domain-cells = <0>;
|
||||
|
||||
pd_a2us: a2us@19 {
|
||||
reg = <19>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pd_a3sm: a3sm@20 {
|
||||
reg = <20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#power-domain-cells = <0>;
|
||||
|
||||
pd_a2sl: a2sl@21 {
|
||||
reg = <21>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pd_a3km: a3km@22 {
|
||||
reg = <22>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#power-domain-cells = <0>;
|
||||
|
||||
pd_a2kl: a2kl@23 {
|
||||
reg = <23>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pd_c4ma: c4ma@1 {
|
||||
reg = <1>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_c4cl: c4cl@2 {
|
||||
reg = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_d4: d4@3 {
|
||||
reg = <3>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_a4bc: a4bc@4 {
|
||||
reg = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#power-domain-cells = <0>;
|
||||
|
||||
pd_a3bc: a3bc@5 {
|
||||
reg = <5>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pd_a4l: a4l@6 {
|
||||
reg = <6>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_a4lc: a4lc@7 {
|
||||
reg = <7>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_a4mp: a4mp@8 {
|
||||
reg = <8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#power-domain-cells = <0>;
|
||||
|
||||
pd_a3mp: a3mp@9 {
|
||||
reg = <9>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_a3vc: a3vc@10 {
|
||||
reg = <10>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pd_a4sf: a4sf@11 {
|
||||
reg = <11>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_a3r: a3r@12 {
|
||||
reg = <12>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#power-domain-cells = <0>;
|
||||
|
||||
pd_a2rv: a2rv@13 {
|
||||
reg = <13>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_a2is: a2is@14 {
|
||||
reg = <14>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,109 +0,0 @@
|
|||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=16
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_PERF_EVENTS=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_ARCH_SHMOBILE_LEGACY=y
|
||||
CONFIG_ARCH_R8A73A4=y
|
||||
CONFIG_MACH_APE6EVM=y
|
||||
# CONFIG_ARM_THUMB is not set
|
||||
CONFIG_CPU_BPREDICT_DISABLE=y
|
||||
CONFIG_PL310_ERRATA_588369=y
|
||||
CONFIG_ARM_ERRATA_754322=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SCHED_MC=y
|
||||
CONFIG_HAVE_ARM_ARCH_TIMER=y
|
||||
CONFIG_NR_CPUS=8
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_HIGHPTE=y
|
||||
# CONFIG_HW_PERF_EVENTS is not set
|
||||
# CONFIG_COMPACTION is not set
|
||||
# CONFIG_CROSS_MEMORY_ATTACH is not set
|
||||
CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
CONFIG_BINFMT_MISC=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=y
|
||||
CONFIG_NET_KEY=y
|
||||
CONFIG_NET_KEY_MIGRATE=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
# CONFIG_INET_LRO is not set
|
||||
# CONFIG_IPV6_SIT is not set
|
||||
CONFIG_NETFILTER=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_FW_LOADER_USER_HELPER is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_CADENCE is not set
|
||||
CONFIG_SMC91X=y
|
||||
CONFIG_SMSC911X=y
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
CONFIG_SERIAL_NONSTANDARD=y
|
||||
CONFIG_SERIAL_SH_SCI=y
|
||||
CONFIG_SERIAL_SH_SCI_NR_UARTS=12
|
||||
CONFIG_SERIAL_SH_SCI_CONSOLE=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_SH_MOBILE=y
|
||||
CONFIG_GPIO_SH_PFC=y
|
||||
CONFIG_GPIOLIB=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_RCAR_THERMAL=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_MAX8973=y
|
||||
# CONFIG_HID is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_SDHI=y
|
||||
CONFIG_MMC_SH_MMCIF=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_SH_DMAE=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
# CONFIG_DNOTIFY is not set
|
||||
CONFIG_TMPFS=y
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3_ACL=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_NFS_V4_1=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_ENABLE_DEFAULT_TRACERS=y
|
||||
CONFIG_CRYPTO_CBC=y
|
||||
CONFIG_CRYPTO_ECB=y
|
||||
CONFIG_CRYPTO_MD5=y
|
||||
CONFIG_CRYPTO_MICHAEL_MIC=y
|
||||
CONFIG_CRYPTO_TWOFISH=y
|
||||
CONFIG_CRC_CCITT=y
|
||||
CONFIG_CRC16=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_CRC_ITU_T=y
|
||||
CONFIG_CRC7=y
|
||||
CONFIG_LIBCRC32C=y
|
||||
|
|
@ -105,13 +105,6 @@ config ARCH_SH73A0
|
|||
select SH_INTC
|
||||
select RENESAS_INTC_IRQPIN
|
||||
|
||||
config ARCH_R8A73A4
|
||||
bool "R-Mobile APE6 (R8A73A40)"
|
||||
select ARCH_RMOBILE
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
select ARM_GIC
|
||||
select RENESAS_IRQC
|
||||
|
||||
config ARCH_R8A7740
|
||||
bool "R-Mobile A1 (R8A77400)"
|
||||
select ARCH_RMOBILE
|
||||
|
|
@ -133,24 +126,6 @@ config ARCH_R8A7779
|
|||
|
||||
comment "Renesas ARM SoCs Board Type"
|
||||
|
||||
config MACH_APE6EVM
|
||||
bool "APE6EVM board"
|
||||
depends on ARCH_R8A73A4
|
||||
select SMSC_PHY if SMSC911X
|
||||
select USE_OF
|
||||
|
||||
config MACH_APE6EVM_REFERENCE
|
||||
bool "APE6EVM board - Reference Device Tree Implementation"
|
||||
depends on ARCH_R8A73A4
|
||||
select SMSC_PHY if SMSC911X
|
||||
select USE_OF
|
||||
---help---
|
||||
Use reference implementation of APE6EVM board support
|
||||
which makes a greater use of device tree at the expense
|
||||
of not supporting a number of devices.
|
||||
|
||||
This is intended to aid developers
|
||||
|
||||
config MACH_ARMADILLO800EVA
|
||||
bool "Armadillo-800 EVA board"
|
||||
depends on ARCH_R8A7740
|
||||
|
|
|
|||
|
|
@ -21,7 +21,6 @@ obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o
|
|||
ifndef CONFIG_COMMON_CLK
|
||||
obj-y += clock.o
|
||||
obj-$(CONFIG_ARCH_SH73A0) += clock-sh73a0.o
|
||||
obj-$(CONFIG_ARCH_R8A73A4) += clock-r8a73a4.o
|
||||
obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o
|
||||
obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o
|
||||
obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o
|
||||
|
|
@ -53,8 +52,6 @@ obj-$(CONFIG_PM_RMOBILE) += pm-rmobile.o
|
|||
ifdef CONFIG_ARCH_SHMOBILE_MULTI
|
||||
obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o
|
||||
else
|
||||
obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o
|
||||
obj-$(CONFIG_MACH_APE6EVM_REFERENCE) += board-ape6evm-reference.o
|
||||
obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
|
||||
obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o
|
||||
obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
# per-board load address for uImage
|
||||
loadaddr-y :=
|
||||
loadaddr-$(CONFIG_MACH_APE6EVM) += 0x40008000
|
||||
loadaddr-$(CONFIG_MACH_APE6EVM_REFERENCE) += 0x40008000
|
||||
loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000
|
||||
loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
|
||||
loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
|
||||
|
|
|
|||
|
|
@ -1,60 +0,0 @@
|
|||
/*
|
||||
* APE6EVM board support
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/sh_clk.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "r8a73a4.h"
|
||||
|
||||
static void __init ape6evm_add_standard_devices(void)
|
||||
{
|
||||
|
||||
struct clk *parent;
|
||||
struct clk *mp;
|
||||
|
||||
r8a73a4_clock_init();
|
||||
|
||||
/* MP clock parent = extal2 */
|
||||
parent = clk_get(NULL, "extal2");
|
||||
mp = clk_get(NULL, "mp");
|
||||
BUG_ON(IS_ERR(parent) || IS_ERR(mp));
|
||||
|
||||
clk_set_parent(mp, parent);
|
||||
clk_put(parent);
|
||||
clk_put(mp);
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static const char *ape6evm_boards_compat_dt[] __initdata = {
|
||||
"renesas,ape6evm-reference",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(APE6EVM_DT, "ape6evm")
|
||||
.init_early = shmobile_init_delay,
|
||||
.init_machine = ape6evm_add_standard_devices,
|
||||
.init_late = shmobile_init_late,
|
||||
.dt_compat = ape6evm_boards_compat_dt,
|
||||
MACHINE_END
|
||||
|
|
@ -1,306 +0,0 @@
|
|||
/*
|
||||
* APE6EVM board support
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mfd/tmio.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/mmc/sh_mmcif.h>
|
||||
#include <linux/mmc/sh_mobile_sdhi.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/smsc911x.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "irqs.h"
|
||||
#include "r8a73a4.h"
|
||||
|
||||
/* LEDS */
|
||||
static struct gpio_led ape6evm_leds[] = {
|
||||
{
|
||||
.name = "gnss-en",
|
||||
.gpio = 28,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
}, {
|
||||
.name = "nfc-nrst",
|
||||
.gpio = 126,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
}, {
|
||||
.name = "gnss-nrst",
|
||||
.gpio = 132,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
}, {
|
||||
.name = "bt-wakeup",
|
||||
.gpio = 232,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
}, {
|
||||
.name = "strobe",
|
||||
.gpio = 250,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
}, {
|
||||
.name = "bbresetout",
|
||||
.gpio = 288,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
},
|
||||
};
|
||||
|
||||
static __initdata struct gpio_led_platform_data ape6evm_leds_pdata = {
|
||||
.leds = ape6evm_leds,
|
||||
.num_leds = ARRAY_SIZE(ape6evm_leds),
|
||||
};
|
||||
|
||||
/* GPIO KEY */
|
||||
#define GPIO_KEY(c, g, d, ...) \
|
||||
{ .code = c, .gpio = g, .desc = d, .active_low = 1 }
|
||||
|
||||
static struct gpio_keys_button gpio_buttons[] = {
|
||||
GPIO_KEY(KEY_0, 324, "S16"),
|
||||
GPIO_KEY(KEY_MENU, 325, "S17"),
|
||||
GPIO_KEY(KEY_HOME, 326, "S18"),
|
||||
GPIO_KEY(KEY_BACK, 327, "S19"),
|
||||
GPIO_KEY(KEY_VOLUMEUP, 328, "S20"),
|
||||
GPIO_KEY(KEY_VOLUMEDOWN, 329, "S21"),
|
||||
};
|
||||
|
||||
static struct gpio_keys_platform_data ape6evm_keys_pdata __initdata = {
|
||||
.buttons = gpio_buttons,
|
||||
.nbuttons = ARRAY_SIZE(gpio_buttons),
|
||||
};
|
||||
|
||||
/* Dummy supplies, where voltage doesn't matter */
|
||||
static struct regulator_consumer_supply dummy_supplies[] = {
|
||||
REGULATOR_SUPPLY("vddvario", "smsc911x"),
|
||||
REGULATOR_SUPPLY("vdd33a", "smsc911x"),
|
||||
};
|
||||
|
||||
/* SMSC LAN9220 */
|
||||
static const struct resource lan9220_res[] __initconst = {
|
||||
DEFINE_RES_MEM(0x08000000, 0x1000),
|
||||
{
|
||||
.start = irq_pin(40), /* IRQ40 */
|
||||
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct smsc911x_platform_config lan9220_data __initconst = {
|
||||
.flags = SMSC911X_USE_32BIT,
|
||||
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
|
||||
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
|
||||
};
|
||||
|
||||
/*
|
||||
* MMC0 power supplies:
|
||||
* Both Vcc and VccQ to eMMC on APE6EVM are supplied by a tps80032 voltage
|
||||
* regulator. Until support for it is added to this file we simulate the
|
||||
* Vcc supply by a fixed always-on regulator
|
||||
*/
|
||||
static struct regulator_consumer_supply vcc_mmc0_consumers[] =
|
||||
{
|
||||
REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
|
||||
};
|
||||
|
||||
/*
|
||||
* SDHI0 power supplies:
|
||||
* Vcc to SDHI0 on APE6EVM is supplied by a GPIO-switchable regulator. VccQ is
|
||||
* provided by the same tps80032 regulator as both MMC0 voltages - see comment
|
||||
* above
|
||||
*/
|
||||
static struct regulator_consumer_supply vcc_sdhi0_consumers[] =
|
||||
{
|
||||
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data vcc_sdhi0_init_data = {
|
||||
.constraints = {
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(vcc_sdhi0_consumers),
|
||||
.consumer_supplies = vcc_sdhi0_consumers,
|
||||
};
|
||||
|
||||
static const struct fixed_voltage_config vcc_sdhi0_info __initconst = {
|
||||
.supply_name = "SDHI0 Vcc",
|
||||
.microvolts = 3300000,
|
||||
.gpio = 76,
|
||||
.enable_high = 1,
|
||||
.init_data = &vcc_sdhi0_init_data,
|
||||
};
|
||||
|
||||
/*
|
||||
* SDHI1 power supplies:
|
||||
* Vcc and VccQ to SDHI1 on APE6EVM are both fixed at 3.3V
|
||||
*/
|
||||
static struct regulator_consumer_supply vcc_sdhi1_consumers[] =
|
||||
{
|
||||
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
|
||||
};
|
||||
|
||||
/* MMCIF */
|
||||
static const struct sh_mmcif_plat_data mmcif0_pdata __initconst = {
|
||||
.caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
|
||||
.slave_id_tx = SHDMA_SLAVE_MMCIF0_TX,
|
||||
.slave_id_rx = SHDMA_SLAVE_MMCIF0_RX,
|
||||
.ccs_unsupported = true,
|
||||
};
|
||||
|
||||
static const struct resource mmcif0_resources[] __initconst = {
|
||||
DEFINE_RES_MEM(0xee200000, 0x100),
|
||||
DEFINE_RES_IRQ(gic_spi(169)),
|
||||
};
|
||||
|
||||
/* SDHI0 */
|
||||
static const struct sh_mobile_sdhi_info sdhi0_pdata __initconst = {
|
||||
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE,
|
||||
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
|
||||
};
|
||||
|
||||
static const struct resource sdhi0_resources[] __initconst = {
|
||||
DEFINE_RES_MEM(0xee100000, 0x100),
|
||||
DEFINE_RES_IRQ(gic_spi(165)),
|
||||
};
|
||||
|
||||
/* SDHI1 */
|
||||
static const struct sh_mobile_sdhi_info sdhi1_pdata __initconst = {
|
||||
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE,
|
||||
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
|
||||
MMC_CAP_NEEDS_POLL,
|
||||
};
|
||||
|
||||
static const struct resource sdhi1_resources[] __initconst = {
|
||||
DEFINE_RES_MEM(0xee120000, 0x100),
|
||||
DEFINE_RES_IRQ(gic_spi(166)),
|
||||
};
|
||||
|
||||
static const struct pinctrl_map ape6evm_pinctrl_map[] __initconst = {
|
||||
/* SCIFA0 console */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4",
|
||||
"scifa0_data", "scifa0"),
|
||||
/* SMSC */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a73a4",
|
||||
"irqc_irq40", "irqc"),
|
||||
/* MMCIF0 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a73a4",
|
||||
"mmc0_data8", "mmc0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a73a4",
|
||||
"mmc0_ctrl", "mmc0"),
|
||||
/* SDHI0: uSD: no WP */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4",
|
||||
"sdhi0_data4", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4",
|
||||
"sdhi0_ctrl", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4",
|
||||
"sdhi0_cd", "sdhi0"),
|
||||
/* SDHI1 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a73a4",
|
||||
"sdhi1_data4", "sdhi1"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a73a4",
|
||||
"sdhi1_ctrl", "sdhi1"),
|
||||
};
|
||||
|
||||
static void __init ape6evm_add_standard_devices(void)
|
||||
{
|
||||
|
||||
struct clk *parent;
|
||||
struct clk *mp;
|
||||
|
||||
r8a73a4_clock_init();
|
||||
|
||||
/* MP clock parent = extal2 */
|
||||
parent = clk_get(NULL, "extal2");
|
||||
mp = clk_get(NULL, "mp");
|
||||
BUG_ON(IS_ERR(parent) || IS_ERR(mp));
|
||||
|
||||
clk_set_parent(mp, parent);
|
||||
clk_put(parent);
|
||||
clk_put(mp);
|
||||
|
||||
pinctrl_register_mappings(ape6evm_pinctrl_map,
|
||||
ARRAY_SIZE(ape6evm_pinctrl_map));
|
||||
r8a73a4_pinmux_init();
|
||||
r8a73a4_add_standard_devices();
|
||||
|
||||
/* LAN9220 ethernet */
|
||||
gpio_request_one(270, GPIOF_OUT_INIT_HIGH, NULL); /* smsc9220 RESET */
|
||||
|
||||
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
|
||||
|
||||
platform_device_register_resndata(NULL, "smsc911x", -1,
|
||||
lan9220_res, ARRAY_SIZE(lan9220_res),
|
||||
&lan9220_data, sizeof(lan9220_data));
|
||||
|
||||
regulator_register_always_on(1, "MMC0 Vcc", vcc_mmc0_consumers,
|
||||
ARRAY_SIZE(vcc_mmc0_consumers), 2800000);
|
||||
platform_device_register_resndata(NULL, "sh_mmcif", 0,
|
||||
mmcif0_resources, ARRAY_SIZE(mmcif0_resources),
|
||||
&mmcif0_pdata, sizeof(mmcif0_pdata));
|
||||
platform_device_register_data(NULL, "reg-fixed-voltage", 2,
|
||||
&vcc_sdhi0_info, sizeof(vcc_sdhi0_info));
|
||||
platform_device_register_resndata(NULL, "sh_mobile_sdhi", 0,
|
||||
sdhi0_resources, ARRAY_SIZE(sdhi0_resources),
|
||||
&sdhi0_pdata, sizeof(sdhi0_pdata));
|
||||
regulator_register_always_on(3, "SDHI1 Vcc", vcc_sdhi1_consumers,
|
||||
ARRAY_SIZE(vcc_sdhi1_consumers), 3300000);
|
||||
platform_device_register_resndata(NULL, "sh_mobile_sdhi", 1,
|
||||
sdhi1_resources, ARRAY_SIZE(sdhi1_resources),
|
||||
&sdhi1_pdata, sizeof(sdhi1_pdata));
|
||||
platform_device_register_data(NULL, "gpio-keys", -1,
|
||||
&ape6evm_keys_pdata,
|
||||
sizeof(ape6evm_keys_pdata));
|
||||
platform_device_register_data(NULL, "leds-gpio", -1,
|
||||
&ape6evm_leds_pdata,
|
||||
sizeof(ape6evm_leds_pdata));
|
||||
}
|
||||
|
||||
static void __init ape6evm_legacy_init_time(void)
|
||||
{
|
||||
/* Do not invoke DT-based timers via clocksource_of_init() */
|
||||
}
|
||||
|
||||
static void __init ape6evm_legacy_init_irq(void)
|
||||
{
|
||||
void __iomem *gic_dist_base = ioremap_nocache(0xf1001000, 0x1000);
|
||||
void __iomem *gic_cpu_base = ioremap_nocache(0xf1002000, 0x1000);
|
||||
|
||||
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
||||
|
||||
/* Do not invoke DT-based interrupt code via irqchip_init() */
|
||||
}
|
||||
|
||||
|
||||
static const char *ape6evm_boards_compat_dt[] __initdata = {
|
||||
"renesas,ape6evm",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(APE6EVM_DT, "ape6evm")
|
||||
.init_early = shmobile_init_delay,
|
||||
.init_irq = ape6evm_legacy_init_irq,
|
||||
.init_machine = ape6evm_add_standard_devices,
|
||||
.init_late = shmobile_init_late,
|
||||
.dt_compat = ape6evm_boards_compat_dt,
|
||||
.init_time = ape6evm_legacy_init_time,
|
||||
MACHINE_END
|
||||
|
|
@ -1,659 +0,0 @@
|
|||
/*
|
||||
* r8a73a4 clock framework support
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include "common.h"
|
||||
#include "clock.h"
|
||||
|
||||
#define CPG_BASE 0xe6150000
|
||||
#define CPG_LEN 0x270
|
||||
|
||||
#define SMSTPCR2 0xe6150138
|
||||
#define SMSTPCR3 0xe615013c
|
||||
#define SMSTPCR4 0xe6150140
|
||||
#define SMSTPCR5 0xe6150144
|
||||
|
||||
#define FRQCRA 0xE6150000
|
||||
#define FRQCRB 0xE6150004
|
||||
#define FRQCRC 0xE61500E0
|
||||
#define VCLKCR1 0xE6150008
|
||||
#define VCLKCR2 0xE615000C
|
||||
#define VCLKCR3 0xE615001C
|
||||
#define VCLKCR4 0xE6150014
|
||||
#define VCLKCR5 0xE6150034
|
||||
#define ZBCKCR 0xE6150010
|
||||
#define SD0CKCR 0xE6150074
|
||||
#define SD1CKCR 0xE6150078
|
||||
#define SD2CKCR 0xE615007C
|
||||
#define MMC0CKCR 0xE6150240
|
||||
#define MMC1CKCR 0xE6150244
|
||||
#define FSIACKCR 0xE6150018
|
||||
#define FSIBCKCR 0xE6150090
|
||||
#define MPCKCR 0xe6150080
|
||||
#define SPUVCKCR 0xE6150094
|
||||
#define HSICKCR 0xE615026C
|
||||
#define M4CKCR 0xE6150098
|
||||
#define PLLECR 0xE61500D0
|
||||
#define PLL0CR 0xE61500D8
|
||||
#define PLL1CR 0xE6150028
|
||||
#define PLL2CR 0xE615002C
|
||||
#define PLL2SCR 0xE61501F4
|
||||
#define PLL2HCR 0xE61501E4
|
||||
#define CKSCR 0xE61500C0
|
||||
|
||||
#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base)
|
||||
|
||||
static struct clk_mapping cpg_mapping = {
|
||||
.phys = CPG_BASE,
|
||||
.len = CPG_LEN,
|
||||
};
|
||||
|
||||
static struct clk extalr_clk = {
|
||||
.rate = 32768,
|
||||
.mapping = &cpg_mapping,
|
||||
};
|
||||
|
||||
static struct clk extal1_clk = {
|
||||
.rate = 26000000,
|
||||
.mapping = &cpg_mapping,
|
||||
};
|
||||
|
||||
static struct clk extal2_clk = {
|
||||
.rate = 48000000,
|
||||
.mapping = &cpg_mapping,
|
||||
};
|
||||
|
||||
static struct sh_clk_ops followparent_clk_ops = {
|
||||
.recalc = followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk main_clk = {
|
||||
/* .parent will be set r8a73a4_clock_init */
|
||||
.ops = &followparent_clk_ops,
|
||||
};
|
||||
|
||||
SH_CLK_RATIO(div2, 1, 2);
|
||||
SH_CLK_RATIO(div4, 1, 4);
|
||||
|
||||
SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2);
|
||||
SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2);
|
||||
SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2);
|
||||
SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_clk, div4);
|
||||
|
||||
/* External FSIACK/FSIBCK clock */
|
||||
static struct clk fsiack_clk = {
|
||||
};
|
||||
|
||||
static struct clk fsibck_clk = {
|
||||
};
|
||||
|
||||
/*
|
||||
* PLL clocks
|
||||
*/
|
||||
static struct clk *pll_parent_main[] = {
|
||||
[0] = &main_clk,
|
||||
[1] = &main_div2_clk
|
||||
};
|
||||
|
||||
static struct clk *pll_parent_main_extal[8] = {
|
||||
[0] = &main_div2_clk,
|
||||
[1] = &extal2_div2_clk,
|
||||
[3] = &extal2_div4_clk,
|
||||
[4] = &main_clk,
|
||||
[5] = &extal2_clk,
|
||||
};
|
||||
|
||||
static unsigned long pll_recalc(struct clk *clk)
|
||||
{
|
||||
unsigned long mult = 1;
|
||||
|
||||
if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit))
|
||||
mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1);
|
||||
|
||||
return clk->parent->rate * mult;
|
||||
}
|
||||
|
||||
static int pll_set_parent(struct clk *clk, struct clk *parent)
|
||||
{
|
||||
u32 val;
|
||||
int i, ret;
|
||||
|
||||
if (!clk->parent_table || !clk->parent_num)
|
||||
return -EINVAL;
|
||||
|
||||
/* Search the parent */
|
||||
for (i = 0; i < clk->parent_num; i++)
|
||||
if (clk->parent_table[i] == parent)
|
||||
break;
|
||||
|
||||
if (i == clk->parent_num)
|
||||
return -ENODEV;
|
||||
|
||||
ret = clk_reparent(clk, parent);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
val = ioread32(clk->mapped_reg) &
|
||||
~(((1 << clk->src_width) - 1) << clk->src_shift);
|
||||
|
||||
iowrite32(val | i << clk->src_shift, clk->mapped_reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops pll_clk_ops = {
|
||||
.recalc = pll_recalc,
|
||||
.set_parent = pll_set_parent,
|
||||
};
|
||||
|
||||
#define PLL_CLOCK(name, p, pt, w, s, reg, e) \
|
||||
static struct clk name = { \
|
||||
.ops = &pll_clk_ops, \
|
||||
.flags = CLK_ENABLE_ON_INIT, \
|
||||
.parent = p, \
|
||||
.parent_table = pt, \
|
||||
.parent_num = ARRAY_SIZE(pt), \
|
||||
.src_width = w, \
|
||||
.src_shift = s, \
|
||||
.enable_reg = (void __iomem *)reg, \
|
||||
.enable_bit = e, \
|
||||
.mapping = &cpg_mapping, \
|
||||
}
|
||||
|
||||
PLL_CLOCK(pll0_clk, &main_clk, pll_parent_main, 1, 20, PLL0CR, 0);
|
||||
PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1);
|
||||
PLL_CLOCK(pll2_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR, 2);
|
||||
PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
|
||||
PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
|
||||
|
||||
SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
|
||||
|
||||
static atomic_t frqcr_lock;
|
||||
|
||||
/* Several clocks need to access FRQCRB, have to lock */
|
||||
static bool frqcr_kick_check(struct clk *clk)
|
||||
{
|
||||
return !(ioread32(CPG_MAP(FRQCRB)) & BIT(31));
|
||||
}
|
||||
|
||||
static int frqcr_kick_do(struct clk *clk)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* set KICK bit in FRQCRB to update hardware setting, check success */
|
||||
iowrite32(ioread32(CPG_MAP(FRQCRB)) | BIT(31), CPG_MAP(FRQCRB));
|
||||
for (i = 1000; i; i--)
|
||||
if (ioread32(CPG_MAP(FRQCRB)) & BIT(31))
|
||||
cpu_relax();
|
||||
else
|
||||
return 0;
|
||||
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static int zclk_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
void __iomem *frqcrc;
|
||||
int ret;
|
||||
unsigned long step, p_rate;
|
||||
u32 val;
|
||||
|
||||
if (!clk->parent || !__clk_get(clk->parent))
|
||||
return -ENODEV;
|
||||
|
||||
if (!atomic_inc_and_test(&frqcr_lock) || !frqcr_kick_check(clk)) {
|
||||
ret = -EBUSY;
|
||||
goto done;
|
||||
}
|
||||
|
||||
/*
|
||||
* Users are supposed to first call clk_set_rate() only with
|
||||
* clk_round_rate() results. So, we don't fix wrong rates here, but
|
||||
* guard against them anyway
|
||||
*/
|
||||
|
||||
p_rate = clk_get_rate(clk->parent);
|
||||
if (rate == p_rate) {
|
||||
val = 0;
|
||||
} else {
|
||||
step = DIV_ROUND_CLOSEST(p_rate, 32);
|
||||
|
||||
if (rate > p_rate || rate < step) {
|
||||
ret = -EINVAL;
|
||||
goto done;
|
||||
}
|
||||
|
||||
val = 32 - rate / step;
|
||||
}
|
||||
|
||||
frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
|
||||
|
||||
iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) |
|
||||
(val << clk->enable_bit), frqcrc);
|
||||
|
||||
ret = frqcr_kick_do(clk);
|
||||
|
||||
done:
|
||||
atomic_dec(&frqcr_lock);
|
||||
__clk_put(clk->parent);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static long zclk_round_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
/*
|
||||
* theoretical rate = parent rate * multiplier / 32,
|
||||
* where 1 <= multiplier <= 32. Therefore we should do
|
||||
* multiplier = rate * 32 / parent rate
|
||||
* rounded rate = parent rate * multiplier / 32.
|
||||
* However, multiplication before division won't fit in 32 bits, so
|
||||
* we sacrifice some precision by first dividing and then multiplying.
|
||||
* To find the nearest divisor we calculate both and pick up the best
|
||||
* one. This avoids 64-bit arithmetics.
|
||||
*/
|
||||
unsigned long step, mul_min, mul_max, rate_min, rate_max;
|
||||
|
||||
rate_max = clk_get_rate(clk->parent);
|
||||
|
||||
/* output freq <= parent */
|
||||
if (rate >= rate_max)
|
||||
return rate_max;
|
||||
|
||||
step = DIV_ROUND_CLOSEST(rate_max, 32);
|
||||
/* output freq >= parent / 32 */
|
||||
if (step >= rate)
|
||||
return step;
|
||||
|
||||
mul_min = rate / step;
|
||||
mul_max = DIV_ROUND_UP(rate, step);
|
||||
rate_min = step * mul_min;
|
||||
if (mul_max == mul_min)
|
||||
return rate_min;
|
||||
|
||||
rate_max = step * mul_max;
|
||||
|
||||
if (rate_max - rate < rate - rate_min)
|
||||
return rate_max;
|
||||
|
||||
return rate_min;
|
||||
}
|
||||
|
||||
static unsigned long zclk_recalc(struct clk *clk)
|
||||
{
|
||||
void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg;
|
||||
unsigned int max = clk->div_mask + 1;
|
||||
unsigned long val = ((ioread32(frqcrc) >> clk->enable_bit) &
|
||||
clk->div_mask);
|
||||
|
||||
return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), max) *
|
||||
(max - val);
|
||||
}
|
||||
|
||||
static struct sh_clk_ops zclk_ops = {
|
||||
.recalc = zclk_recalc,
|
||||
.set_rate = zclk_set_rate,
|
||||
.round_rate = zclk_round_rate,
|
||||
};
|
||||
|
||||
static struct clk z_clk = {
|
||||
.parent = &pll0_clk,
|
||||
.div_mask = 0x1f,
|
||||
.enable_bit = 8,
|
||||
/* We'll need to access FRQCRB and FRQCRC */
|
||||
.enable_reg = (void __iomem *)FRQCRB,
|
||||
.ops = &zclk_ops,
|
||||
};
|
||||
|
||||
/*
|
||||
* It seems only 1/2 divider is usable in manual mode. 1/2 / 2/3
|
||||
* switching is only available in auto-DVFS mode
|
||||
*/
|
||||
SH_FIXED_RATIO_CLK(pll0_div2_clk, pll0_clk, div2);
|
||||
|
||||
static struct clk z2_clk = {
|
||||
.parent = &pll0_div2_clk,
|
||||
.div_mask = 0x1f,
|
||||
.enable_bit = 0,
|
||||
/* We'll need to access FRQCRB and FRQCRC */
|
||||
.enable_reg = (void __iomem *)FRQCRB,
|
||||
.ops = &zclk_ops,
|
||||
};
|
||||
|
||||
static struct clk *main_clks[] = {
|
||||
&extalr_clk,
|
||||
&extal1_clk,
|
||||
&extal1_div2_clk,
|
||||
&extal2_clk,
|
||||
&extal2_div2_clk,
|
||||
&extal2_div4_clk,
|
||||
&main_clk,
|
||||
&main_div2_clk,
|
||||
&fsiack_clk,
|
||||
&fsibck_clk,
|
||||
&pll0_clk,
|
||||
&pll1_clk,
|
||||
&pll1_div2_clk,
|
||||
&pll2_clk,
|
||||
&pll2s_clk,
|
||||
&pll2h_clk,
|
||||
&z_clk,
|
||||
&pll0_div2_clk,
|
||||
&z2_clk,
|
||||
};
|
||||
|
||||
/* DIV4 */
|
||||
static void div4_kick(struct clk *clk)
|
||||
{
|
||||
if (!WARN(!atomic_inc_and_test(&frqcr_lock), "FRQCR* lock broken!\n"))
|
||||
frqcr_kick_do(clk);
|
||||
atomic_dec(&frqcr_lock);
|
||||
}
|
||||
|
||||
static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
|
||||
|
||||
static struct clk_div_mult_table div4_div_mult_table = {
|
||||
.divisors = divisors,
|
||||
.nr_divisors = ARRAY_SIZE(divisors),
|
||||
};
|
||||
|
||||
static struct clk_div4_table div4_table = {
|
||||
.div_mult_table = &div4_div_mult_table,
|
||||
.kick = div4_kick,
|
||||
};
|
||||
|
||||
enum {
|
||||
DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
|
||||
DIV4_ZX, DIV4_ZS, DIV4_HP,
|
||||
DIV4_NR };
|
||||
|
||||
static struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_I] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_M3] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 8, 0x0dff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_M1] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 4, 0x1dff, 0),
|
||||
[DIV4_M2] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 0, 0x1dff, 0),
|
||||
[DIV4_ZX] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0),
|
||||
[DIV4_ZS] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 8, 0x0dff, 0),
|
||||
[DIV4_HP] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 4, 0x0dff, 0),
|
||||
};
|
||||
|
||||
enum {
|
||||
DIV6_ZB,
|
||||
DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
|
||||
DIV6_MMC0, DIV6_MMC1,
|
||||
DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5,
|
||||
DIV6_FSIA, DIV6_FSIB,
|
||||
DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV,
|
||||
DIV6_NR };
|
||||
|
||||
static struct clk *div6_parents[8] = {
|
||||
[0] = &pll1_div2_clk,
|
||||
[1] = &pll2s_clk,
|
||||
[3] = &extal2_clk,
|
||||
[4] = &main_div2_clk,
|
||||
[6] = &extalr_clk,
|
||||
};
|
||||
|
||||
static struct clk *fsia_parents[4] = {
|
||||
[0] = &pll1_div2_clk,
|
||||
[1] = &pll2s_clk,
|
||||
[2] = &fsiack_clk,
|
||||
};
|
||||
|
||||
static struct clk *fsib_parents[4] = {
|
||||
[0] = &pll1_div2_clk,
|
||||
[1] = &pll2s_clk,
|
||||
[2] = &fsibck_clk,
|
||||
};
|
||||
|
||||
static struct clk *mp_parents[4] = {
|
||||
[0] = &pll1_div2_clk,
|
||||
[1] = &pll2s_clk,
|
||||
[2] = &extal2_clk,
|
||||
[3] = &extal2_clk,
|
||||
};
|
||||
|
||||
static struct clk *m4_parents[2] = {
|
||||
[0] = &pll2s_clk,
|
||||
};
|
||||
|
||||
static struct clk *hsi_parents[4] = {
|
||||
[0] = &pll2h_clk,
|
||||
[1] = &pll1_div2_clk,
|
||||
[3] = &pll2s_clk,
|
||||
};
|
||||
|
||||
/*** FIXME ***
|
||||
* SH_CLK_DIV6_EXT() macro doesn't care .mapping
|
||||
* but, it is necessary on R-Car (= ioremap() base CPG)
|
||||
* The difference between
|
||||
* SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT()
|
||||
* is only .mapping
|
||||
*/
|
||||
#define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents, \
|
||||
_num_parents, _src_shift, _src_width) \
|
||||
{ \
|
||||
.enable_reg = (void __iomem *)_reg, \
|
||||
.enable_bit = 0, /* unused */ \
|
||||
.flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
|
||||
.div_mask = SH_CLK_DIV6_MSK, \
|
||||
.parent_table = _parents, \
|
||||
.parent_num = _num_parents, \
|
||||
.src_shift = _src_shift, \
|
||||
.src_width = _src_width, \
|
||||
.mapping = &cpg_mapping, \
|
||||
}
|
||||
|
||||
static struct clk div6_clks[DIV6_NR] = {
|
||||
[DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
|
||||
div6_parents, 2, 7, 1),
|
||||
[DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0,
|
||||
div6_parents, 2, 6, 2),
|
||||
[DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0,
|
||||
div6_parents, 2, 6, 2),
|
||||
[DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0,
|
||||
div6_parents, 2, 6, 2),
|
||||
[DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0,
|
||||
div6_parents, 2, 6, 2),
|
||||
[DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0,
|
||||
div6_parents, 2, 6, 2),
|
||||
[DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0, /* didn't care bit[6-7] */
|
||||
div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
|
||||
[DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0, /* didn't care bit[6-7] */
|
||||
div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
|
||||
[DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0, /* didn't care bit[6-7] */
|
||||
div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
|
||||
[DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0, /* didn't care bit[6-7] */
|
||||
div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
|
||||
[DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0, /* didn't care bit[6-7] */
|
||||
div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
|
||||
[DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0,
|
||||
fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
|
||||
[DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0,
|
||||
fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
|
||||
[DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0, /* it needs bit[9-11] control */
|
||||
mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
|
||||
/* pll2s will be selected always for M4 */
|
||||
[DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0, /* it needs bit[9] control */
|
||||
m4_parents, ARRAY_SIZE(m4_parents), 6, 1),
|
||||
[DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0, /* it needs bit[9] control */
|
||||
hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2),
|
||||
[DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0,
|
||||
mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
|
||||
};
|
||||
|
||||
/* MSTP */
|
||||
enum {
|
||||
MSTP218, MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
|
||||
MSTP329, MSTP323, MSTP318, MSTP317, MSTP316,
|
||||
MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
|
||||
MSTP411, MSTP410, MSTP409,
|
||||
MSTP522, MSTP515,
|
||||
MSTP_NR
|
||||
};
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 4, 0), /* SCIFA0 */
|
||||
[MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 3, 0), /* SCIFA1 */
|
||||
[MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 6, 0), /* SCIFB0 */
|
||||
[MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */
|
||||
[MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */
|
||||
[MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */
|
||||
[MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC */
|
||||
[MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0), /* IIC2 */
|
||||
[MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
|
||||
[MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
|
||||
[MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */
|
||||
[MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */
|
||||
[MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */
|
||||
[MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 16, 0), /* IIC6 */
|
||||
[MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 17, 0), /* IIC7 */
|
||||
[MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* IIC0 */
|
||||
[MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
|
||||
[MSTP329] = SH_CLK_MSTP32(&extalr_clk, SMSTPCR3, 29, 0), /* CMT10 */
|
||||
[MSTP409] = SH_CLK_MSTP32(&main_div2_clk, SMSTPCR4, 9, 0), /* IIC5 */
|
||||
[MSTP410] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
|
||||
[MSTP411] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
|
||||
[MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
|
||||
[MSTP515] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR5, 15, 0), /* IIC8 */
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clock */
|
||||
CLKDEV_CON_ID("extal1", &extal1_clk),
|
||||
CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk),
|
||||
CLKDEV_CON_ID("extal2", &extal2_clk),
|
||||
CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk),
|
||||
CLKDEV_CON_ID("extal2_div4", &extal2_div4_clk),
|
||||
CLKDEV_CON_ID("fsiack", &fsiack_clk),
|
||||
CLKDEV_CON_ID("fsibck", &fsibck_clk),
|
||||
|
||||
/* pll clock */
|
||||
CLKDEV_CON_ID("pll1", &pll1_clk),
|
||||
CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
|
||||
CLKDEV_CON_ID("pll2", &pll2_clk),
|
||||
CLKDEV_CON_ID("pll2s", &pll2s_clk),
|
||||
CLKDEV_CON_ID("pll2h", &pll2h_clk),
|
||||
|
||||
/* CPU clock */
|
||||
CLKDEV_DEV_ID("cpu0", &z_clk),
|
||||
|
||||
/* DIV6 */
|
||||
CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]),
|
||||
CLKDEV_CON_ID("vck1", &div6_clks[DIV6_VCK1]),
|
||||
CLKDEV_CON_ID("vck2", &div6_clks[DIV6_VCK2]),
|
||||
CLKDEV_CON_ID("vck3", &div6_clks[DIV6_VCK3]),
|
||||
CLKDEV_CON_ID("vck4", &div6_clks[DIV6_VCK4]),
|
||||
CLKDEV_CON_ID("vck5", &div6_clks[DIV6_VCK5]),
|
||||
CLKDEV_CON_ID("fsia", &div6_clks[DIV6_FSIA]),
|
||||
CLKDEV_CON_ID("fsib", &div6_clks[DIV6_FSIB]),
|
||||
CLKDEV_CON_ID("mp", &div6_clks[DIV6_MP]),
|
||||
CLKDEV_CON_ID("m4", &div6_clks[DIV6_M4]),
|
||||
CLKDEV_CON_ID("hsi", &div6_clks[DIV6_HSI]),
|
||||
CLKDEV_CON_ID("spuv", &div6_clks[DIV6_SPUV]),
|
||||
|
||||
/* MSTP */
|
||||
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
|
||||
CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]),
|
||||
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
|
||||
CLKDEV_DEV_ID("e6c50000.serial", &mstp_clks[MSTP203]),
|
||||
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
|
||||
CLKDEV_DEV_ID("e6c20000.serial", &mstp_clks[MSTP206]),
|
||||
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
|
||||
CLKDEV_DEV_ID("e6c30000.serial", &mstp_clks[MSTP207]),
|
||||
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
|
||||
CLKDEV_DEV_ID("e6ce0000.serial", &mstp_clks[MSTP216]),
|
||||
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
|
||||
CLKDEV_DEV_ID("e6cf0000.serial", &mstp_clks[MSTP217]),
|
||||
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
|
||||
CLKDEV_DEV_ID("e6700020.dma-controller", &mstp_clks[MSTP218]),
|
||||
CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
|
||||
CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
|
||||
CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
|
||||
CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]),
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
|
||||
CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]),
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
|
||||
CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]),
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
|
||||
CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
|
||||
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
|
||||
CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
|
||||
CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]),
|
||||
CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]),
|
||||
CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]),
|
||||
CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]),
|
||||
CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.1", &mstp_clks[MSTP329]),
|
||||
CLKDEV_ICK_ID("fck", "e6130000.timer", &mstp_clks[MSTP329]),
|
||||
CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]),
|
||||
CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]),
|
||||
CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]),
|
||||
CLKDEV_DEV_ID("e6570000.i2c", &mstp_clks[MSTP515]),
|
||||
|
||||
/* for DT */
|
||||
CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
|
||||
};
|
||||
|
||||
void __init r8a73a4_clock_init(void)
|
||||
{
|
||||
void __iomem *reg;
|
||||
int k, ret = 0;
|
||||
u32 ckscr;
|
||||
|
||||
atomic_set(&frqcr_lock, -1);
|
||||
|
||||
reg = ioremap_nocache(CKSCR, PAGE_SIZE);
|
||||
BUG_ON(!reg);
|
||||
ckscr = ioread32(reg);
|
||||
iounmap(reg);
|
||||
|
||||
switch ((ckscr >> 28) & 0x3) {
|
||||
case 0:
|
||||
main_clk.parent = &extal1_clk;
|
||||
break;
|
||||
case 1:
|
||||
main_clk.parent = &extal1_div2_clk;
|
||||
break;
|
||||
case 2:
|
||||
main_clk.parent = &extal2_clk;
|
||||
break;
|
||||
case 3:
|
||||
main_clk.parent = &extal2_div2_clk;
|
||||
break;
|
||||
}
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||
ret = clk_register(main_clks[k]);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
if (!ret)
|
||||
shmobile_clk_init();
|
||||
else
|
||||
panic("failed to setup r8a73a4 clocks\n");
|
||||
}
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
#ifndef __ASM_R8A73A4_H__
|
||||
#define __ASM_R8A73A4_H__
|
||||
|
||||
/* DMA slave IDs */
|
||||
enum {
|
||||
SHDMA_SLAVE_INVALID,
|
||||
SHDMA_SLAVE_MMCIF0_TX,
|
||||
SHDMA_SLAVE_MMCIF0_RX,
|
||||
SHDMA_SLAVE_MMCIF1_TX,
|
||||
SHDMA_SLAVE_MMCIF1_RX,
|
||||
};
|
||||
|
||||
void r8a73a4_add_standard_devices(void);
|
||||
void r8a73a4_clock_init(void);
|
||||
void r8a73a4_pinmux_init(void);
|
||||
|
||||
#endif /* __ASM_R8A73A4_H__ */
|
||||
|
|
@ -13,280 +13,12 @@
|
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#include <linux/irq.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_data/irq-renesas-irqc.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/sh_dma.h>
|
||||
#include <linux/sh_timer.h>
|
||||
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "dma-register.h"
|
||||
#include "irqs.h"
|
||||
#include "r8a73a4.h"
|
||||
|
||||
static const struct resource pfc_resources[] = {
|
||||
DEFINE_RES_MEM(0xe6050000, 0x9000),
|
||||
};
|
||||
|
||||
void __init r8a73a4_pinmux_init(void)
|
||||
{
|
||||
platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources,
|
||||
ARRAY_SIZE(pfc_resources));
|
||||
}
|
||||
|
||||
#define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq) \
|
||||
static struct plat_sci_port scif##index##_platform_data = { \
|
||||
.type = scif_type, \
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
|
||||
.scscr = _scscr, \
|
||||
}; \
|
||||
\
|
||||
static struct resource scif##index##_resources[] = { \
|
||||
DEFINE_RES_MEM(baseaddr, 0x100), \
|
||||
DEFINE_RES_IRQ(irq), \
|
||||
}
|
||||
|
||||
#define R8A73A4_SCIFA(index, baseaddr, irq) \
|
||||
R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
|
||||
index, baseaddr, irq)
|
||||
|
||||
#define R8A73A4_SCIFB(index, baseaddr, irq) \
|
||||
R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
|
||||
index, baseaddr, irq)
|
||||
|
||||
R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
|
||||
R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
|
||||
R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
|
||||
R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
|
||||
R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
|
||||
R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */
|
||||
|
||||
#define r8a73a4_register_scif(index) \
|
||||
platform_device_register_resndata(NULL, "sh-sci", index, \
|
||||
scif##index##_resources, \
|
||||
ARRAY_SIZE(scif##index##_resources), \
|
||||
&scif##index##_platform_data, \
|
||||
sizeof(scif##index##_platform_data))
|
||||
|
||||
static const struct renesas_irqc_config irqc0_data = {
|
||||
.irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
|
||||
};
|
||||
|
||||
static const struct resource irqc0_resources[] = {
|
||||
DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
|
||||
DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
|
||||
DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
|
||||
DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
|
||||
DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
|
||||
DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
|
||||
DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
|
||||
DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
|
||||
DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
|
||||
DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
|
||||
DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
|
||||
DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
|
||||
DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
|
||||
DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
|
||||
DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
|
||||
DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
|
||||
DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
|
||||
DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
|
||||
DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
|
||||
DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
|
||||
DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
|
||||
DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
|
||||
DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
|
||||
DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
|
||||
DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
|
||||
DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
|
||||
DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
|
||||
DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
|
||||
DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
|
||||
DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
|
||||
DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
|
||||
DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
|
||||
DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
|
||||
};
|
||||
|
||||
static const struct renesas_irqc_config irqc1_data = {
|
||||
.irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
|
||||
};
|
||||
|
||||
static const struct resource irqc1_resources[] = {
|
||||
DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
|
||||
DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
|
||||
DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
|
||||
DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
|
||||
DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
|
||||
DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
|
||||
DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
|
||||
DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
|
||||
DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
|
||||
DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
|
||||
DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
|
||||
DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
|
||||
DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
|
||||
DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
|
||||
DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
|
||||
DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
|
||||
DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
|
||||
DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
|
||||
DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
|
||||
DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
|
||||
DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
|
||||
DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
|
||||
DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
|
||||
DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
|
||||
DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
|
||||
DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
|
||||
DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
|
||||
};
|
||||
|
||||
#define r8a73a4_register_irqc(idx) \
|
||||
platform_device_register_resndata(NULL, "renesas_irqc", \
|
||||
idx, irqc##idx##_resources, \
|
||||
ARRAY_SIZE(irqc##idx##_resources), \
|
||||
&irqc##idx##_data, \
|
||||
sizeof(struct renesas_irqc_config))
|
||||
|
||||
/* Thermal0 -> Thermal2 */
|
||||
static const struct resource thermal0_resources[] = {
|
||||
DEFINE_RES_MEM(0xe61f0000, 0x14),
|
||||
DEFINE_RES_MEM(0xe61f0100, 0x38),
|
||||
DEFINE_RES_MEM(0xe61f0200, 0x38),
|
||||
DEFINE_RES_MEM(0xe61f0300, 0x38),
|
||||
DEFINE_RES_IRQ(gic_spi(69)),
|
||||
};
|
||||
|
||||
#define r8a73a4_register_thermal() \
|
||||
platform_device_register_simple("rcar_thermal", -1, \
|
||||
thermal0_resources, \
|
||||
ARRAY_SIZE(thermal0_resources))
|
||||
|
||||
static struct sh_timer_config cmt1_platform_data = {
|
||||
.channels_mask = 0xff,
|
||||
};
|
||||
|
||||
static struct resource cmt1_resources[] = {
|
||||
DEFINE_RES_MEM(0xe6130000, 0x1004),
|
||||
DEFINE_RES_IRQ(gic_spi(120)),
|
||||
};
|
||||
|
||||
#define r8a73a4_register_cmt(idx) \
|
||||
platform_device_register_resndata(NULL, "sh-cmt-48-gen2", \
|
||||
idx, cmt##idx##_resources, \
|
||||
ARRAY_SIZE(cmt##idx##_resources), \
|
||||
&cmt##idx##_platform_data, \
|
||||
sizeof(struct sh_timer_config))
|
||||
|
||||
/* DMA */
|
||||
static const struct sh_dmae_slave_config dma_slaves[] = {
|
||||
{
|
||||
.slave_id = SHDMA_SLAVE_MMCIF0_TX,
|
||||
.addr = 0xee200034,
|
||||
.chcr = CHCR_TX(XMIT_SZ_32BIT),
|
||||
.mid_rid = 0xd1,
|
||||
}, {
|
||||
.slave_id = SHDMA_SLAVE_MMCIF0_RX,
|
||||
.addr = 0xee200034,
|
||||
.chcr = CHCR_RX(XMIT_SZ_32BIT),
|
||||
.mid_rid = 0xd2,
|
||||
}, {
|
||||
.slave_id = SHDMA_SLAVE_MMCIF1_TX,
|
||||
.addr = 0xee220034,
|
||||
.chcr = CHCR_TX(XMIT_SZ_32BIT),
|
||||
.mid_rid = 0xe1,
|
||||
}, {
|
||||
.slave_id = SHDMA_SLAVE_MMCIF1_RX,
|
||||
.addr = 0xee220034,
|
||||
.chcr = CHCR_RX(XMIT_SZ_32BIT),
|
||||
.mid_rid = 0xe2,
|
||||
},
|
||||
};
|
||||
|
||||
#define DMAE_CHANNEL(a, b) \
|
||||
{ \
|
||||
.offset = (a) - 0x20, \
|
||||
.dmars = (a) - 0x20 + 0x40, \
|
||||
.chclr_bit = (b), \
|
||||
.chclr_offset = 0x80 - 0x20, \
|
||||
}
|
||||
|
||||
static const struct sh_dmae_channel dma_channels[] = {
|
||||
DMAE_CHANNEL(0x8000, 0),
|
||||
DMAE_CHANNEL(0x8080, 1),
|
||||
DMAE_CHANNEL(0x8100, 2),
|
||||
DMAE_CHANNEL(0x8180, 3),
|
||||
DMAE_CHANNEL(0x8200, 4),
|
||||
DMAE_CHANNEL(0x8280, 5),
|
||||
DMAE_CHANNEL(0x8300, 6),
|
||||
DMAE_CHANNEL(0x8380, 7),
|
||||
DMAE_CHANNEL(0x8400, 8),
|
||||
DMAE_CHANNEL(0x8480, 9),
|
||||
DMAE_CHANNEL(0x8500, 10),
|
||||
DMAE_CHANNEL(0x8580, 11),
|
||||
DMAE_CHANNEL(0x8600, 12),
|
||||
DMAE_CHANNEL(0x8680, 13),
|
||||
DMAE_CHANNEL(0x8700, 14),
|
||||
DMAE_CHANNEL(0x8780, 15),
|
||||
DMAE_CHANNEL(0x8800, 16),
|
||||
DMAE_CHANNEL(0x8880, 17),
|
||||
DMAE_CHANNEL(0x8900, 18),
|
||||
DMAE_CHANNEL(0x8980, 19),
|
||||
};
|
||||
|
||||
static const struct sh_dmae_pdata dma_pdata = {
|
||||
.slave = dma_slaves,
|
||||
.slave_num = ARRAY_SIZE(dma_slaves),
|
||||
.channel = dma_channels,
|
||||
.channel_num = ARRAY_SIZE(dma_channels),
|
||||
.ts_low_shift = TS_LOW_SHIFT,
|
||||
.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
|
||||
.ts_high_shift = TS_HI_SHIFT,
|
||||
.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
|
||||
.ts_shift = dma_ts_shift,
|
||||
.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
|
||||
.dmaor_init = DMAOR_DME,
|
||||
.chclr_present = 1,
|
||||
.chclr_bitwise = 1,
|
||||
};
|
||||
|
||||
static struct resource dma_resources[] = {
|
||||
DEFINE_RES_MEM(0xe6700020, 0x89e0),
|
||||
DEFINE_RES_IRQ(gic_spi(220)),
|
||||
{
|
||||
/* IRQ for channels 0-19 */
|
||||
.start = gic_spi(200),
|
||||
.end = gic_spi(219),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
#define r8a73a4_register_dmac() \
|
||||
platform_device_register_resndata(NULL, "sh-dma-engine", 0, \
|
||||
dma_resources, ARRAY_SIZE(dma_resources), \
|
||||
&dma_pdata, sizeof(dma_pdata))
|
||||
|
||||
void __init r8a73a4_add_standard_devices(void)
|
||||
{
|
||||
r8a73a4_register_cmt(1);
|
||||
r8a73a4_register_scif(0);
|
||||
r8a73a4_register_scif(1);
|
||||
r8a73a4_register_scif(2);
|
||||
r8a73a4_register_scif(3);
|
||||
r8a73a4_register_scif(4);
|
||||
r8a73a4_register_scif(5);
|
||||
r8a73a4_register_irqc(0);
|
||||
r8a73a4_register_irqc(1);
|
||||
r8a73a4_register_thermal();
|
||||
r8a73a4_register_dmac();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USE_OF
|
||||
|
||||
static const char *r8a73a4_boards_compat_dt[] __initdata = {
|
||||
"renesas,r8a73a4",
|
||||
|
|
@ -298,4 +30,3 @@ DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
|
|||
.init_late = shmobile_init_late,
|
||||
.dt_compat = r8a73a4_boards_compat_dt,
|
||||
MACHINE_END
|
||||
#endif /* CONFIG_USE_OF */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* Copyright 2014 Ulrich Hecht
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A73A4_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A73A4_H__
|
||||
|
||||
/* CPG */
|
||||
#define R8A73A4_CLK_MAIN 0
|
||||
#define R8A73A4_CLK_PLL0 1
|
||||
#define R8A73A4_CLK_PLL1 2
|
||||
#define R8A73A4_CLK_PLL2 3
|
||||
#define R8A73A4_CLK_PLL2S 4
|
||||
#define R8A73A4_CLK_PLL2H 5
|
||||
#define R8A73A4_CLK_Z 6
|
||||
#define R8A73A4_CLK_Z2 7
|
||||
#define R8A73A4_CLK_I 8
|
||||
#define R8A73A4_CLK_M3 9
|
||||
#define R8A73A4_CLK_B 10
|
||||
#define R8A73A4_CLK_M1 11
|
||||
#define R8A73A4_CLK_M2 12
|
||||
#define R8A73A4_CLK_ZX 13
|
||||
#define R8A73A4_CLK_ZS 14
|
||||
#define R8A73A4_CLK_HP 15
|
||||
|
||||
/* MSTP2 */
|
||||
#define R8A73A4_CLK_DMAC 18
|
||||
#define R8A73A4_CLK_SCIFB3 17
|
||||
#define R8A73A4_CLK_SCIFB2 16
|
||||
#define R8A73A4_CLK_SCIFB1 7
|
||||
#define R8A73A4_CLK_SCIFB0 6
|
||||
#define R8A73A4_CLK_SCIFA0 4
|
||||
#define R8A73A4_CLK_SCIFA1 3
|
||||
|
||||
/* MSTP3 */
|
||||
#define R8A73A4_CLK_CMT1 29
|
||||
#define R8A73A4_CLK_IIC1 23
|
||||
#define R8A73A4_CLK_IIC0 18
|
||||
#define R8A73A4_CLK_IIC7 17
|
||||
#define R8A73A4_CLK_IIC6 16
|
||||
#define R8A73A4_CLK_MMCIF0 15
|
||||
#define R8A73A4_CLK_SDHI0 14
|
||||
#define R8A73A4_CLK_SDHI1 13
|
||||
#define R8A73A4_CLK_SDHI2 12
|
||||
#define R8A73A4_CLK_MMCIF1 5
|
||||
#define R8A73A4_CLK_IIC2 0
|
||||
|
||||
/* MSTP4 */
|
||||
#define R8A73A4_CLK_IIC3 11
|
||||
#define R8A73A4_CLK_IIC4 10
|
||||
#define R8A73A4_CLK_IIC5 9
|
||||
|
||||
/* MSTP5 */
|
||||
#define R8A73A4_CLK_THERMAL 22
|
||||
#define R8A73A4_CLK_IIC8 15
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A73A4_H__ */
|
||||
Loading…
Reference in New Issue