mirror of https://gitee.com/openkylin/linux.git
MIPS: cleanup fixup_bigphys_addr handling
fixup_bigphys_addr is only provided by the alchemy platform. Remove all the stubs, and ensure we only call it if it is actually implemented. Also don't bother implementing io_remap_pfn_range if we don't have to, and move the remaining implementation to alchemy platform code. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Christoph Hellwig
Thomas Bogendoerfer
parent
b604d4973a
commit
d399157283
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@ -92,6 +92,9 @@ config MIPS
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select SYSCTL_EXCEPTION_TRACE
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select VIRT_TO_BUS
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config MIPS_FIXUP_BIGPHYS_ADDR
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bool
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menu "Machine selection"
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choice
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@ -157,6 +160,7 @@ config MIPS_ALCHEMY
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select CSRC_R4K
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select IRQ_MIPS_CPU
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select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
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select MIPS_FIXUP_BIGPHYS_ADDR if PCI
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_APM_EMULATION
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@ -72,9 +72,9 @@ void __init plat_mem_setup(void)
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iomem_resource.end = IOMEM_RESOURCE_END;
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}
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#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI)
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#ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR
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/* This routine should be valid for all Au1x based boards */
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phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
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phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
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{
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unsigned long start = ALCHEMY_PCI_MEMWIN_START;
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unsigned long end = ALCHEMY_PCI_MEMWIN_END;
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@ -90,5 +90,13 @@ phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
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/* default nop */
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return phys_addr;
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}
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EXPORT_SYMBOL(__fixup_bigphys_addr);
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#endif
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int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long vaddr,
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unsigned long pfn, unsigned long size, pgprot_t prot)
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{
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phys_addr_t phys_addr = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
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return remap_pfn_range(vma, vaddr, phys_addr >> PAGE_SHIFT, size, prot);
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}
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EXPORT_SYMBOL(io_remap_pfn_range);
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#endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */
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@ -1,38 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* include/asm-mips/mach-au1x00/ioremap.h
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*/
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#ifndef __ASM_MACH_AU1X00_IOREMAP_H
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#define __ASM_MACH_AU1X00_IOREMAP_H
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#include <linux/types.h>
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#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI)
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extern phys_addr_t __fixup_bigphys_addr(phys_addr_t, phys_addr_t);
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#else
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static inline phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
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{
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return phys_addr;
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}
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#endif
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/*
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* Allow physical addresses to be fixed up to help 36-bit peripherals.
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*/
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static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
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{
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return __fixup_bigphys_addr(phys_addr, size);
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}
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static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
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unsigned long flags)
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{
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return NULL;
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}
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static inline int plat_iounmap(const volatile void __iomem *addr)
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{
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return 0;
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}
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#endif /* __ASM_MACH_AU1X00_IOREMAP_H */
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@ -4,11 +4,6 @@
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#include <bcm63xx_cpu.h>
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static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
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{
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return phys_addr;
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}
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static inline int is_bcm63xx_internal_registers(phys_addr_t offset)
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{
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switch (bcm63xx_get_cpu_id()) {
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@ -4,11 +4,6 @@
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#include <linux/types.h>
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static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
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{
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return phys_addr;
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}
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static inline int is_bmips_internal_registers(phys_addr_t offset)
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{
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if (offset >= 0xfff80000)
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@ -7,15 +7,6 @@
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#include <linux/types.h>
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/*
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* Allow physical addresses to be fixed up to help peripherals located
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* outside the low 32-bit range -- generic pass-through version.
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*/
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static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
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{
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return phys_addr;
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}
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static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
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unsigned long flags)
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{
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@ -7,15 +7,6 @@
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#include <linux/types.h>
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/*
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* Allow physical addresses to be fixed up to help peripherals located
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* outside the low 32-bit range -- generic pass-through version.
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*/
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static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
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{
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return phys_addr;
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}
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static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
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unsigned long flags)
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{
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@ -7,15 +7,6 @@
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#include <linux/types.h>
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/*
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* Allow physical addresses to be fixed up to help peripherals located
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* outside the low 32-bit range -- generic pass-through version.
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*/
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static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
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{
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return phys_addr;
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}
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static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
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unsigned long flags)
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{
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@ -507,20 +507,17 @@ static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
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#define kern_addr_valid(addr) (1)
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
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extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot);
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static inline int io_remap_pfn_range(struct vm_area_struct *vma,
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unsigned long vaddr,
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unsigned long pfn,
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unsigned long size,
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pgprot_t prot)
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{
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phys_addr_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
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return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot);
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}
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/*
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* Allow physical addresses to be fixed up to help 36-bit peripherals.
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*/
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#ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR
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phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size);
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int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long vaddr,
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unsigned long pfn, unsigned long size, pgprot_t prot);
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#define io_remap_pfn_range io_remap_pfn_range
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#endif
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#else
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#define fixup_bigphys_addr(addr, size) (addr)
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#endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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@ -52,7 +52,7 @@ struct alchemy_pci_context {
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static struct alchemy_pci_context *__alchemy_pci_ctx;
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/* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr
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/* IO/MEM resources for PCI. Keep the memres in sync with fixup_bigphys_addr
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* in arch/mips/alchemy/common/setup.c
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*/
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static struct resource alchemy_pci_def_memres = {
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