mirror of https://gitee.com/openkylin/linux.git
drm/hisilicon: Add plane driver for ADE
Add plane funcs and helper funcs for ADE. v8: None. v7: None. v6: None. v5: None. v4: None. v3: - A few cleanup. v2: - Remove abtraction layer. Signed-off-by: Xinliang Liu <xinliang.liu@linaro.org> Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
This commit is contained in:
Xinliang Liu
parent
783ad972c9
commit
d3c9a7385f
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@ -27,13 +27,23 @@
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_plane_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include "kirin_drm_drv.h"
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#include "kirin_ade_reg.h"
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#define PRIMARY_CH ADE_CH1 /* primary plane */
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#define OUT_OVLY ADE_OVLY2 /* output overlay compositor */
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#define ADE_DEBUG 1
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#define to_ade_crtc(crtc) \
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container_of(crtc, struct ade_crtc, base)
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#define to_ade_plane(plane) \
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container_of(plane, struct ade_plane, base)
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struct ade_hw_ctx {
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void __iomem *base;
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struct regmap *noc_regmap;
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@ -52,11 +62,76 @@ struct ade_crtc {
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u32 out_format;
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};
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struct ade_plane {
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struct drm_plane base;
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void *ctx;
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u8 ch; /* channel */
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};
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struct ade_data {
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struct ade_crtc acrtc;
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struct ade_plane aplane[ADE_CH_NUM];
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struct ade_hw_ctx ctx;
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};
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/* ade-format info: */
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struct ade_format {
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u32 pixel_format;
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enum ade_fb_format ade_format;
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};
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static const struct ade_format ade_formats[] = {
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/* 16bpp RGB: */
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{ DRM_FORMAT_RGB565, ADE_RGB_565 },
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{ DRM_FORMAT_BGR565, ADE_BGR_565 },
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/* 24bpp RGB: */
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{ DRM_FORMAT_RGB888, ADE_RGB_888 },
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{ DRM_FORMAT_BGR888, ADE_BGR_888 },
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/* 32bpp [A]RGB: */
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{ DRM_FORMAT_XRGB8888, ADE_XRGB_8888 },
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{ DRM_FORMAT_XBGR8888, ADE_XBGR_8888 },
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{ DRM_FORMAT_RGBA8888, ADE_RGBA_8888 },
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{ DRM_FORMAT_BGRA8888, ADE_BGRA_8888 },
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{ DRM_FORMAT_ARGB8888, ADE_ARGB_8888 },
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{ DRM_FORMAT_ABGR8888, ADE_ABGR_8888 },
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};
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static const u32 channel_formats1[] = {
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/* channel 1,2,3,4 */
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DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888,
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DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888,
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DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888,
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DRM_FORMAT_ABGR8888
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};
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u32 ade_get_channel_formats(u8 ch, const u32 **formats)
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{
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switch (ch) {
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case ADE_CH1:
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*formats = channel_formats1;
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return ARRAY_SIZE(channel_formats1);
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default:
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DRM_ERROR("no this channel %d\n", ch);
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*formats = NULL;
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return 0;
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}
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}
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/* convert from fourcc format to ade format */
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static u32 ade_get_format(u32 pixel_format)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(ade_formats); i++)
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if (ade_formats[i].pixel_format == pixel_format)
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return ade_formats[i].ade_format;
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/* not found */
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DRM_ERROR("Not found pixel format!!fourcc_format= %d\n",
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pixel_format);
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return ADE_FORMAT_UNSUPPORT;
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}
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static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val)
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{
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u32 bit_ofst, reg_num;
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@ -89,7 +164,7 @@ static void ade_init(struct ade_hw_ctx *ctx)
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/* clear overlay */
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writel(0, base + ADE_OVLY1_TRANS_CFG);
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writel(0, base + ADE_OVLY_CTL);
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writel(0, base + ADE_OVLYX_CTL(ADE_OVLY2));
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writel(0, base + ADE_OVLYX_CTL(OUT_OVLY));
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/* clear reset and reload regs */
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writel(MASK(32), base + ADE_SOFT_RST_SEL(0));
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writel(MASK(32), base + ADE_SOFT_RST_SEL(1));
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@ -155,6 +230,10 @@ static void ade_ldi_set_mode(struct ade_crtc *acrtc,
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base + LDI_DSP_SIZE);
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writel(plr_flags, base + LDI_PLR_CTRL);
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/* set overlay compositor output size */
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writel(((width - 1) << OUTPUT_XSIZE_OFST) | (height - 1),
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base + ADE_OVLY_OUTPUT_SIZE(OUT_OVLY));
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/* ctran6 setting */
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writel(CTRAN_BYPASS_ON, base + ADE_CTRAN_DIS(ADE_CTRAN6));
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/* the configured value is actual value - 1 */
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@ -229,6 +308,10 @@ static void ade_display_enable(struct ade_crtc *acrtc)
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void __iomem *base = ctx->base;
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u32 out_fmt = acrtc->out_format;
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/* enable output overlay compositor */
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writel(ADE_ENABLE, base + ADE_OVLYX_CTL(OUT_OVLY));
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ade_update_reload_bit(base, OVLY_OFST + OUT_OVLY, 0);
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/* display source setting */
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writel(DISP_SRC_OVLY2, base + ADE_DISP_SRC_CFG);
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@ -242,6 +325,97 @@ static void ade_display_enable(struct ade_crtc *acrtc)
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writel(DSI_PCLK_ON, base + LDI_HDMI_DSI_GT);
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}
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#if ADE_DEBUG
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static void ade_rdma_dump_regs(void __iomem *base, u32 ch)
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{
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u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en;
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u32 val;
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reg_ctrl = RD_CH_CTRL(ch);
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reg_addr = RD_CH_ADDR(ch);
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reg_size = RD_CH_SIZE(ch);
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reg_stride = RD_CH_STRIDE(ch);
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reg_space = RD_CH_SPACE(ch);
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reg_en = RD_CH_EN(ch);
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val = ade_read_reload_bit(base, RDMA_OFST + ch);
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DRM_DEBUG_DRIVER("[rdma%d]: reload(%d)\n", ch + 1, val);
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val = readl(base + reg_ctrl);
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DRM_DEBUG_DRIVER("[rdma%d]: reg_ctrl(0x%08x)\n", ch + 1, val);
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val = readl(base + reg_addr);
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DRM_DEBUG_DRIVER("[rdma%d]: reg_addr(0x%08x)\n", ch + 1, val);
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val = readl(base + reg_size);
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DRM_DEBUG_DRIVER("[rdma%d]: reg_size(0x%08x)\n", ch + 1, val);
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val = readl(base + reg_stride);
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DRM_DEBUG_DRIVER("[rdma%d]: reg_stride(0x%08x)\n", ch + 1, val);
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val = readl(base + reg_space);
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DRM_DEBUG_DRIVER("[rdma%d]: reg_space(0x%08x)\n", ch + 1, val);
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val = readl(base + reg_en);
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DRM_DEBUG_DRIVER("[rdma%d]: reg_en(0x%08x)\n", ch + 1, val);
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}
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static void ade_clip_dump_regs(void __iomem *base, u32 ch)
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{
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u32 val;
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val = ade_read_reload_bit(base, CLIP_OFST + ch);
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DRM_DEBUG_DRIVER("[clip%d]: reload(%d)\n", ch + 1, val);
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val = readl(base + ADE_CLIP_DISABLE(ch));
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DRM_DEBUG_DRIVER("[clip%d]: reg_clip_disable(0x%08x)\n", ch + 1, val);
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val = readl(base + ADE_CLIP_SIZE0(ch));
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DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size0(0x%08x)\n", ch + 1, val);
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val = readl(base + ADE_CLIP_SIZE1(ch));
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DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size1(0x%08x)\n", ch + 1, val);
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}
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static void ade_compositor_routing_dump_regs(void __iomem *base, u32 ch)
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{
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u8 ovly_ch = 0; /* TODO: Only primary plane now */
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u32 val;
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val = readl(base + ADE_OVLY_CH_XY0(ovly_ch));
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DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy0(0x%08x)\n", ovly_ch, val);
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val = readl(base + ADE_OVLY_CH_XY1(ovly_ch));
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DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy1(0x%08x)\n", ovly_ch, val);
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val = readl(base + ADE_OVLY_CH_CTL(ovly_ch));
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DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_ctl(0x%08x)\n", ovly_ch, val);
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}
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static void ade_dump_overlay_compositor_regs(void __iomem *base, u32 comp)
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{
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u32 val;
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val = ade_read_reload_bit(base, OVLY_OFST + comp);
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DRM_DEBUG_DRIVER("[overlay%d]: reload(%d)\n", comp + 1, val);
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writel(ADE_ENABLE, base + ADE_OVLYX_CTL(comp));
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DRM_DEBUG_DRIVER("[overlay%d]: reg_ctl(0x%08x)\n", comp + 1, val);
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val = readl(base + ADE_OVLY_CTL);
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DRM_DEBUG_DRIVER("ovly_ctl(0x%08x)\n", val);
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}
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static void ade_dump_regs(void __iomem *base)
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{
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u32 i;
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/* dump channel regs */
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for (i = 0; i < ADE_CH_NUM; i++) {
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/* dump rdma regs */
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ade_rdma_dump_regs(base, i);
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/* dump clip regs */
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ade_clip_dump_regs(base, i);
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/* dump compositor routing regs */
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ade_compositor_routing_dump_regs(base, i);
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}
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/* dump overlay compositor regs */
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ade_dump_overlay_compositor_regs(base, OUT_OVLY);
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}
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#else
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static void ade_dump_regs(void __iomem *base) { }
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#endif
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static void ade_crtc_enable(struct drm_crtc *crtc)
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{
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struct ade_crtc *acrtc = to_ade_crtc(crtc);
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@ -259,6 +433,7 @@ static void ade_crtc_enable(struct drm_crtc *crtc)
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ade_set_medianoc_qos(acrtc);
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ade_display_enable(acrtc);
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ade_dump_regs(ctx->base);
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acrtc->enable = true;
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}
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@ -313,6 +488,7 @@ static void ade_crtc_atomic_flush(struct drm_crtc *crtc,
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/* only crtc is enabled regs take effect */
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if (acrtc->enable) {
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ade_dump_regs(base);
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/* flush ade registers */
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writel(ADE_ENABLE, base + ADE_EN);
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}
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@ -369,6 +545,338 @@ static int ade_crtc_init(struct drm_device *dev, struct drm_crtc *crtc,
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return 0;
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}
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static void ade_rdma_set(void __iomem *base, struct drm_framebuffer *fb,
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u32 ch, u32 y, u32 in_h, u32 fmt)
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{
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struct drm_gem_cma_object *obj = drm_fb_cma_get_gem_obj(fb, 0);
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u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en;
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u32 stride = fb->pitches[0];
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u32 addr = (u32)obj->paddr + y * stride;
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DRM_DEBUG_DRIVER("rdma%d: (y=%d, height=%d), stride=%d, paddr=0x%x\n",
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ch + 1, y, in_h, stride, (u32)obj->paddr);
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DRM_DEBUG_DRIVER("addr=0x%x, fb:%dx%d, pixel_format=%d(%s)\n",
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addr, fb->width, fb->height, fmt,
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drm_get_format_name(fb->pixel_format));
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/* get reg offset */
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reg_ctrl = RD_CH_CTRL(ch);
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reg_addr = RD_CH_ADDR(ch);
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reg_size = RD_CH_SIZE(ch);
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reg_stride = RD_CH_STRIDE(ch);
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reg_space = RD_CH_SPACE(ch);
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reg_en = RD_CH_EN(ch);
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/*
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* TODO: set rotation
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*/
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writel((fmt << 16) & 0x1f0000, base + reg_ctrl);
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writel(addr, base + reg_addr);
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writel((in_h << 16) | stride, base + reg_size);
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writel(stride, base + reg_stride);
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writel(in_h * stride, base + reg_space);
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writel(ADE_ENABLE, base + reg_en);
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ade_update_reload_bit(base, RDMA_OFST + ch, 0);
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}
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static void ade_rdma_disable(void __iomem *base, u32 ch)
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{
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u32 reg_en;
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/* get reg offset */
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reg_en = RD_CH_EN(ch);
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writel(0, base + reg_en);
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ade_update_reload_bit(base, RDMA_OFST + ch, 1);
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}
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static void ade_clip_set(void __iomem *base, u32 ch, u32 fb_w, u32 x,
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u32 in_w, u32 in_h)
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{
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u32 disable_val;
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u32 clip_left;
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u32 clip_right;
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/*
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* clip width, no need to clip height
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*/
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if (fb_w == in_w) { /* bypass */
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disable_val = 1;
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clip_left = 0;
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clip_right = 0;
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} else {
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disable_val = 0;
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clip_left = x;
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clip_right = fb_w - (x + in_w) - 1;
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}
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DRM_DEBUG_DRIVER("clip%d: clip_left=%d, clip_right=%d\n",
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ch + 1, clip_left, clip_right);
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writel(disable_val, base + ADE_CLIP_DISABLE(ch));
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writel((fb_w - 1) << 16 | (in_h - 1), base + ADE_CLIP_SIZE0(ch));
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writel(clip_left << 16 | clip_right, base + ADE_CLIP_SIZE1(ch));
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ade_update_reload_bit(base, CLIP_OFST + ch, 0);
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}
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static void ade_clip_disable(void __iomem *base, u32 ch)
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{
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writel(1, base + ADE_CLIP_DISABLE(ch));
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ade_update_reload_bit(base, CLIP_OFST + ch, 1);
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}
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static bool has_Alpha_channel(int format)
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{
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switch (format) {
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case ADE_ARGB_8888:
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case ADE_ABGR_8888:
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case ADE_RGBA_8888:
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case ADE_BGRA_8888:
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return true;
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default:
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return false;
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}
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}
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static void ade_get_blending_params(u32 fmt, u8 glb_alpha, u8 *alp_mode,
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u8 *alp_sel, u8 *under_alp_sel)
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{
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bool has_alpha = has_Alpha_channel(fmt);
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/*
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* get alp_mode
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*/
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if (has_alpha && glb_alpha < 255)
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*alp_mode = ADE_ALP_PIXEL_AND_GLB;
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else if (has_alpha)
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*alp_mode = ADE_ALP_PIXEL;
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else
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*alp_mode = ADE_ALP_GLOBAL;
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/*
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* get alp sel
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*/
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*alp_sel = ADE_ALP_MUL_COEFF_3; /* 1 */
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*under_alp_sel = ADE_ALP_MUL_COEFF_2; /* 0 */
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}
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static void ade_compositor_routing_set(void __iomem *base, u8 ch,
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u32 x0, u32 y0,
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u32 in_w, u32 in_h, u32 fmt)
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{
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u8 ovly_ch = 0; /* TODO: This is the zpos, only one plane now */
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u8 glb_alpha = 255;
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u32 x1 = x0 + in_w - 1;
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u32 y1 = y0 + in_h - 1;
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u32 val;
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u8 alp_sel;
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u8 under_alp_sel;
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u8 alp_mode;
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ade_get_blending_params(fmt, glb_alpha, &alp_mode, &alp_sel,
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&under_alp_sel);
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/* overlay routing setting
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*/
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writel(x0 << 16 | y0, base + ADE_OVLY_CH_XY0(ovly_ch));
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writel(x1 << 16 | y1, base + ADE_OVLY_CH_XY1(ovly_ch));
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val = (ch + 1) << CH_SEL_OFST | BIT(CH_EN_OFST) |
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alp_sel << CH_ALP_SEL_OFST |
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under_alp_sel << CH_UNDER_ALP_SEL_OFST |
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glb_alpha << CH_ALP_GBL_OFST |
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alp_mode << CH_ALP_MODE_OFST;
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writel(val, base + ADE_OVLY_CH_CTL(ovly_ch));
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/* connect this plane/channel to overlay2 compositor */
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ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch),
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CH_OVLY_SEL_MASK, CH_OVLY_SEL_VAL(OUT_OVLY));
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}
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static void ade_compositor_routing_disable(void __iomem *base, u32 ch)
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{
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u8 ovly_ch = 0; /* TODO: Only primary plane now */
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/* disable this plane/channel */
|
||||
ade_update_bits(base + ADE_OVLY_CH_CTL(ovly_ch), CH_EN_OFST,
|
||||
MASK(1), 0);
|
||||
/* dis-connect this plane/channel of overlay2 compositor */
|
||||
ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch),
|
||||
CH_OVLY_SEL_MASK, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Typicaly, a channel looks like: DMA-->clip-->scale-->ctrans-->compositor
|
||||
*/
|
||||
static void ade_update_channel(struct ade_plane *aplane,
|
||||
struct drm_framebuffer *fb, int crtc_x,
|
||||
int crtc_y, unsigned int crtc_w,
|
||||
unsigned int crtc_h, u32 src_x,
|
||||
u32 src_y, u32 src_w, u32 src_h)
|
||||
{
|
||||
struct ade_hw_ctx *ctx = aplane->ctx;
|
||||
void __iomem *base = ctx->base;
|
||||
u32 fmt = ade_get_format(fb->pixel_format);
|
||||
u32 ch = aplane->ch;
|
||||
u32 in_w;
|
||||
u32 in_h;
|
||||
|
||||
DRM_DEBUG_DRIVER("channel%d: src:(%d, %d)-%dx%d, crtc:(%d, %d)-%dx%d",
|
||||
ch + 1, src_x, src_y, src_w, src_h,
|
||||
crtc_x, crtc_y, crtc_w, crtc_h);
|
||||
|
||||
/* 1) DMA setting */
|
||||
in_w = src_w;
|
||||
in_h = src_h;
|
||||
ade_rdma_set(base, fb, ch, src_y, in_h, fmt);
|
||||
|
||||
/* 2) clip setting */
|
||||
ade_clip_set(base, ch, fb->width, src_x, in_w, in_h);
|
||||
|
||||
/* 3) TODO: scale setting for overlay planes */
|
||||
|
||||
/* 4) TODO: ctran/csc setting for overlay planes */
|
||||
|
||||
/* 5) compositor routing setting */
|
||||
ade_compositor_routing_set(base, ch, crtc_x, crtc_y, in_w, in_h, fmt);
|
||||
}
|
||||
|
||||
static void ade_disable_channel(struct ade_plane *aplane)
|
||||
{
|
||||
struct ade_hw_ctx *ctx = aplane->ctx;
|
||||
void __iomem *base = ctx->base;
|
||||
u32 ch = aplane->ch;
|
||||
|
||||
DRM_DEBUG_DRIVER("disable channel%d\n", ch + 1);
|
||||
|
||||
/* disable read DMA */
|
||||
ade_rdma_disable(base, ch);
|
||||
|
||||
/* disable clip */
|
||||
ade_clip_disable(base, ch);
|
||||
|
||||
/* disable compositor routing */
|
||||
ade_compositor_routing_disable(base, ch);
|
||||
}
|
||||
|
||||
static int ade_plane_prepare_fb(struct drm_plane *plane,
|
||||
const struct drm_plane_state *new_state)
|
||||
{
|
||||
/* do nothing */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ade_plane_cleanup_fb(struct drm_plane *plane,
|
||||
const struct drm_plane_state *old_state)
|
||||
{
|
||||
/* do nothing */
|
||||
}
|
||||
|
||||
static int ade_plane_atomic_check(struct drm_plane *plane,
|
||||
struct drm_plane_state *state)
|
||||
{
|
||||
struct drm_framebuffer *fb = state->fb;
|
||||
struct drm_crtc *crtc = state->crtc;
|
||||
struct drm_crtc_state *crtc_state;
|
||||
u32 src_x = state->src_x >> 16;
|
||||
u32 src_y = state->src_y >> 16;
|
||||
u32 src_w = state->src_w >> 16;
|
||||
u32 src_h = state->src_h >> 16;
|
||||
int crtc_x = state->crtc_x;
|
||||
int crtc_y = state->crtc_y;
|
||||
u32 crtc_w = state->crtc_w;
|
||||
u32 crtc_h = state->crtc_h;
|
||||
u32 fmt;
|
||||
|
||||
if (!crtc || !fb)
|
||||
return 0;
|
||||
|
||||
fmt = ade_get_format(fb->pixel_format);
|
||||
if (fmt == ADE_FORMAT_UNSUPPORT)
|
||||
return -EINVAL;
|
||||
|
||||
crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
|
||||
if (IS_ERR(crtc_state))
|
||||
return PTR_ERR(crtc_state);
|
||||
|
||||
if (src_w != crtc_w || src_h != crtc_h) {
|
||||
DRM_ERROR("Scale not support!!!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (src_x + src_w > fb->width ||
|
||||
src_y + src_h > fb->height)
|
||||
return -EINVAL;
|
||||
|
||||
if (crtc_x < 0 || crtc_y < 0)
|
||||
return -EINVAL;
|
||||
|
||||
if (crtc_x + crtc_w > crtc_state->adjusted_mode.hdisplay ||
|
||||
crtc_y + crtc_h > crtc_state->adjusted_mode.vdisplay)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ade_plane_atomic_update(struct drm_plane *plane,
|
||||
struct drm_plane_state *old_state)
|
||||
{
|
||||
struct drm_plane_state *state = plane->state;
|
||||
struct ade_plane *aplane = to_ade_plane(plane);
|
||||
|
||||
ade_update_channel(aplane, state->fb, state->crtc_x, state->crtc_y,
|
||||
state->crtc_w, state->crtc_h,
|
||||
state->src_x >> 16, state->src_y >> 16,
|
||||
state->src_w >> 16, state->src_h >> 16);
|
||||
}
|
||||
|
||||
static void ade_plane_atomic_disable(struct drm_plane *plane,
|
||||
struct drm_plane_state *old_state)
|
||||
{
|
||||
struct ade_plane *aplane = to_ade_plane(plane);
|
||||
|
||||
ade_disable_channel(aplane);
|
||||
}
|
||||
|
||||
static const struct drm_plane_helper_funcs ade_plane_helper_funcs = {
|
||||
.prepare_fb = ade_plane_prepare_fb,
|
||||
.cleanup_fb = ade_plane_cleanup_fb,
|
||||
.atomic_check = ade_plane_atomic_check,
|
||||
.atomic_update = ade_plane_atomic_update,
|
||||
.atomic_disable = ade_plane_atomic_disable,
|
||||
};
|
||||
|
||||
static struct drm_plane_funcs ade_plane_funcs = {
|
||||
.update_plane = drm_atomic_helper_update_plane,
|
||||
.disable_plane = drm_atomic_helper_disable_plane,
|
||||
.set_property = drm_atomic_helper_plane_set_property,
|
||||
.destroy = drm_plane_cleanup,
|
||||
.reset = drm_atomic_helper_plane_reset,
|
||||
.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
|
||||
.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
|
||||
};
|
||||
|
||||
static int ade_plane_init(struct drm_device *dev, struct ade_plane *aplane,
|
||||
enum drm_plane_type type)
|
||||
{
|
||||
const u32 *fmts;
|
||||
u32 fmts_cnt;
|
||||
int ret = 0;
|
||||
|
||||
/* get properties */
|
||||
fmts_cnt = ade_get_channel_formats(aplane->ch, &fmts);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = drm_universal_plane_init(dev, &aplane->base, 1, &ade_plane_funcs,
|
||||
fmts, fmts_cnt, type, NULL);
|
||||
if (ret) {
|
||||
DRM_ERROR("fail to init plane, ch=%d\n", aplane->ch);
|
||||
return ret;
|
||||
}
|
||||
|
||||
drm_plane_helper_add(&aplane->base, &ade_plane_helper_funcs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ade_dts_parse(struct platform_device *pdev, struct ade_hw_ctx *ctx)
|
||||
{
|
||||
struct resource *res;
|
||||
|
|
@ -426,7 +934,10 @@ static int ade_drm_init(struct drm_device *dev)
|
|||
struct ade_data *ade;
|
||||
struct ade_hw_ctx *ctx;
|
||||
struct ade_crtc *acrtc;
|
||||
struct ade_plane *aplane;
|
||||
enum drm_plane_type type;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
ade = devm_kzalloc(dev->dev, sizeof(*ade), GFP_KERNEL);
|
||||
if (!ade) {
|
||||
|
|
@ -444,6 +955,28 @@ static int ade_drm_init(struct drm_device *dev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* plane init
|
||||
* TODO: Now only support primary plane, overlay planes
|
||||
* need to do.
|
||||
*/
|
||||
for (i = 0; i < ADE_CH_NUM; i++) {
|
||||
aplane = &ade->aplane[i];
|
||||
aplane->ch = i;
|
||||
aplane->ctx = ctx;
|
||||
type = i == PRIMARY_CH ? DRM_PLANE_TYPE_PRIMARY :
|
||||
DRM_PLANE_TYPE_OVERLAY;
|
||||
|
||||
ret = ade_plane_init(dev, aplane, type);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* crtc init */
|
||||
ret = ade_crtc_init(dev, &acrtc->base, &ade->aplane[PRIMARY_CH].base);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue