mirror of https://gitee.com/openkylin/linux.git
Merge branch 'net-stmmac-fix-handling-of-oversized-frames'
Aaro Koskinen says: ==================== net: stmmac: fix handling of oversized frames I accidentally had MTU size mismatch (9000 vs. 1500) in my network, and I noticed I could kill a system using stmmac & 1500 MTU simply by pinging it with "ping -s 2000 ...". While testing a fix I encountered also some other issues that need fixing. I have tested these only with enhanced descriptors, so the normal descriptor changes need a careful review. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
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commit
d3de85a51a
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@ -29,11 +29,13 @@
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/* Specific functions used for Ring mode */
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/* Enhanced descriptors */
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static inline void ehn_desc_rx_set_on_ring(struct dma_desc *p, int end)
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static inline void ehn_desc_rx_set_on_ring(struct dma_desc *p, int end,
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int bfsize)
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{
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p->des1 |= cpu_to_le32((BUF_SIZE_8KiB
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<< ERDES1_BUFFER2_SIZE_SHIFT)
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& ERDES1_BUFFER2_SIZE_MASK);
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if (bfsize == BUF_SIZE_16KiB)
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p->des1 |= cpu_to_le32((BUF_SIZE_8KiB
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<< ERDES1_BUFFER2_SIZE_SHIFT)
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& ERDES1_BUFFER2_SIZE_MASK);
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if (end)
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p->des1 |= cpu_to_le32(ERDES1_END_RING);
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@ -59,11 +61,15 @@ static inline void enh_set_tx_desc_len_on_ring(struct dma_desc *p, int len)
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}
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/* Normal descriptors */
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static inline void ndesc_rx_set_on_ring(struct dma_desc *p, int end)
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static inline void ndesc_rx_set_on_ring(struct dma_desc *p, int end, int bfsize)
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{
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p->des1 |= cpu_to_le32(((BUF_SIZE_2KiB - 1)
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<< RDES1_BUFFER2_SIZE_SHIFT)
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& RDES1_BUFFER2_SIZE_MASK);
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if (bfsize >= BUF_SIZE_2KiB) {
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int bfsize2;
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bfsize2 = min(bfsize - BUF_SIZE_2KiB + 1, BUF_SIZE_2KiB - 1);
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p->des1 |= cpu_to_le32((bfsize2 << RDES1_BUFFER2_SIZE_SHIFT)
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& RDES1_BUFFER2_SIZE_MASK);
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}
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if (end)
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p->des1 |= cpu_to_le32(RDES1_END_RING);
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@ -296,7 +296,7 @@ static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc,
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}
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static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
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int mode, int end)
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int mode, int end, int bfsize)
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{
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dwmac4_set_rx_owner(p, disable_rx_ic);
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}
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@ -123,7 +123,7 @@ static int dwxgmac2_get_rx_timestamp_status(void *desc, void *next_desc,
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}
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static void dwxgmac2_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
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int mode, int end)
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int mode, int end, int bfsize)
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{
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dwxgmac2_set_rx_owner(p, disable_rx_ic);
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}
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@ -201,6 +201,11 @@ static int enh_desc_get_rx_status(void *data, struct stmmac_extra_stats *x,
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if (unlikely(rdes0 & RDES0_OWN))
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return dma_own;
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if (unlikely(!(rdes0 & RDES0_LAST_DESCRIPTOR))) {
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stats->rx_length_errors++;
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return discard_frame;
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}
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if (unlikely(rdes0 & RDES0_ERROR_SUMMARY)) {
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if (unlikely(rdes0 & RDES0_DESCRIPTOR_ERROR)) {
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x->rx_desc++;
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@ -231,9 +236,10 @@ static int enh_desc_get_rx_status(void *data, struct stmmac_extra_stats *x,
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* It doesn't match with the information reported into the databook.
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* At any rate, we need to understand if the CSUM hw computation is ok
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* and report this info to the upper layers. */
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ret = enh_desc_coe_rdes0(!!(rdes0 & RDES0_IPC_CSUM_ERROR),
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!!(rdes0 & RDES0_FRAME_TYPE),
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!!(rdes0 & ERDES0_RX_MAC_ADDR));
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if (likely(ret == good_frame))
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ret = enh_desc_coe_rdes0(!!(rdes0 & RDES0_IPC_CSUM_ERROR),
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!!(rdes0 & RDES0_FRAME_TYPE),
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!!(rdes0 & ERDES0_RX_MAC_ADDR));
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if (unlikely(rdes0 & RDES0_DRIBBLING))
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x->dribbling_bit++;
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@ -259,15 +265,19 @@ static int enh_desc_get_rx_status(void *data, struct stmmac_extra_stats *x,
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}
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static void enh_desc_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
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int mode, int end)
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int mode, int end, int bfsize)
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{
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int bfsize1;
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p->des0 |= cpu_to_le32(RDES0_OWN);
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p->des1 |= cpu_to_le32(BUF_SIZE_8KiB & ERDES1_BUFFER1_SIZE_MASK);
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bfsize1 = min(bfsize, BUF_SIZE_8KiB);
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p->des1 |= cpu_to_le32(bfsize1 & ERDES1_BUFFER1_SIZE_MASK);
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if (mode == STMMAC_CHAIN_MODE)
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ehn_desc_rx_set_on_chain(p);
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else
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ehn_desc_rx_set_on_ring(p, end);
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ehn_desc_rx_set_on_ring(p, end, bfsize);
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if (disable_rx_ic)
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p->des1 |= cpu_to_le32(ERDES1_DISABLE_IC);
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@ -33,7 +33,7 @@ struct dma_extended_desc;
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struct stmmac_desc_ops {
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/* DMA RX descriptor ring initialization */
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void (*init_rx_desc)(struct dma_desc *p, int disable_rx_ic, int mode,
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int end);
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int end, int bfsize);
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/* DMA TX descriptor ring initialization */
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void (*init_tx_desc)(struct dma_desc *p, int mode, int end);
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/* Invoked by the xmit function to prepare the tx descriptor */
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@ -91,8 +91,6 @@ static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
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return dma_own;
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if (unlikely(!(rdes0 & RDES0_LAST_DESCRIPTOR))) {
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pr_warn("%s: Oversized frame spanned multiple buffers\n",
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__func__);
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stats->rx_length_errors++;
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return discard_frame;
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}
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@ -135,15 +133,19 @@ static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
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}
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static void ndesc_init_rx_desc(struct dma_desc *p, int disable_rx_ic, int mode,
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int end)
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int end, int bfsize)
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{
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int bfsize1;
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p->des0 |= cpu_to_le32(RDES0_OWN);
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p->des1 |= cpu_to_le32((BUF_SIZE_2KiB - 1) & RDES1_BUFFER1_SIZE_MASK);
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bfsize1 = min(bfsize, BUF_SIZE_2KiB - 1);
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p->des1 |= cpu_to_le32(bfsize & RDES1_BUFFER1_SIZE_MASK);
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if (mode == STMMAC_CHAIN_MODE)
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ndesc_rx_set_on_chain(p, end);
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else
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ndesc_rx_set_on_ring(p, end);
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ndesc_rx_set_on_ring(p, end, bfsize);
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if (disable_rx_ic)
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p->des1 |= cpu_to_le32(RDES1_DISABLE_IC);
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@ -1136,11 +1136,13 @@ static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
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if (priv->extend_desc)
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stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
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priv->use_riwt, priv->mode,
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(i == DMA_RX_SIZE - 1));
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(i == DMA_RX_SIZE - 1),
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priv->dma_buf_sz);
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else
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stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
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priv->use_riwt, priv->mode,
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(i == DMA_RX_SIZE - 1));
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(i == DMA_RX_SIZE - 1),
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priv->dma_buf_sz);
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}
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/**
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@ -3352,9 +3354,8 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
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{
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struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
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struct stmmac_channel *ch = &priv->channel[queue];
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unsigned int entry = rx_q->cur_rx;
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unsigned int next_entry = rx_q->cur_rx;
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int coe = priv->hw->rx_csum;
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unsigned int next_entry;
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unsigned int count = 0;
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bool xmac;
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@ -3372,10 +3373,12 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
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stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
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}
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while (count < limit) {
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int status;
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int entry, status;
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struct dma_desc *p;
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struct dma_desc *np;
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entry = next_entry;
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if (priv->extend_desc)
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p = (struct dma_desc *)(rx_q->dma_erx + entry);
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else
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@ -3431,11 +3434,12 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
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* ignored
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*/
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if (frame_len > priv->dma_buf_sz) {
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netdev_err(priv->dev,
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"len %d larger than size (%d)\n",
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frame_len, priv->dma_buf_sz);
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if (net_ratelimit())
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netdev_err(priv->dev,
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"len %d larger than size (%d)\n",
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frame_len, priv->dma_buf_sz);
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priv->dev->stats.rx_length_errors++;
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break;
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continue;
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}
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/* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
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dev_warn(priv->device,
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"packet dropped\n");
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priv->dev->stats.rx_dropped++;
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break;
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continue;
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}
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dma_sync_single_for_cpu(priv->device,
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} else {
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skb = rx_q->rx_skbuff[entry];
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if (unlikely(!skb)) {
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netdev_err(priv->dev,
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"%s: Inconsistent Rx chain\n",
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priv->dev->name);
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if (net_ratelimit())
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netdev_err(priv->dev,
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"%s: Inconsistent Rx chain\n",
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priv->dev->name);
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priv->dev->stats.rx_dropped++;
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break;
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continue;
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}
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prefetch(skb->data - NET_IP_ALIGN);
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rx_q->rx_skbuff[entry] = NULL;
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priv->dev->stats.rx_packets++;
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priv->dev->stats.rx_bytes += frame_len;
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}
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entry = next_entry;
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}
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stmmac_rx_refill(priv, queue);
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