openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

x86/intel_rdt: Move CBM specific data into a struct 

Memory bandwidth allocation requires different information than cache
allocation.

To avoid a lump of data in struct rdt_resource, move all cache related
information into a seperate structure and add that to struct rdt_resource.

Sanitize the data types while at it.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: ravi.v.shankar@intel.com
Cc: tony.luck@intel.com
Cc: fenghua.yu@intel.com
Cc: vikas.shivappa@intel.com
This commit is contained in:
Thomas Gleixner 2017-04-14 13:00:36 +02:00
parent 2545e9f51e
commit d3e11b4d6f
4 changed files with 83 additions and 65 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
arch/x86/include/asm/intel_rdt.h
View File

@ -73,37 +73,46 @@ struct rftype {
char *buf, size_t nbytes, loff_t off);
};
/**
* struct rdt_cache - Cache allocation related data
* @cbm_len: Length of the cache bit mask
* @min_cbm_bits: Minimum number of consecutive bits to be set
* @cbm_idx_mult: Multiplier of CBM index
* @cbm_idx_offset: Offset of CBM index. CBM index is computed by:
* closid * cbm_idx_multi + cbm_idx_offset
* in a cache bit mask
*/
struct rdt_cache {
unsigned int cbm_len;
unsigned int min_cbm_bits;
unsigned int cbm_idx_mult;
unsigned int cbm_idx_offset;
};
/**
* struct rdt_resource - attributes of an RDT resource
* @enabled: Is this feature enabled on this machine
* @capable: Is this feature available on this machine
* @name: Name to use in "schemata" file
* @num_closid: Number of CLOSIDs available
* @default_ctrl: Specifies default cache cbm or mem b/w percent.
* @data_width: Character width of data when displaying
* @min_cbm_bits: Minimum number of consecutive bits to be set
* in a cache bit mask
* @domains: All domains for this resource
* @msr_base: Base MSR address for CBMs
* @cache_level: Which cache level defines scope of this domain
* @cbm_idx_multi: Multiplier of CBM index
* @cbm_idx_offset: Offset of CBM index. CBM index is computed by:
* closid * cbm_idx_multi + cbm_idx_offset
* @enabled: Is this feature enabled on this machine
* @capable: Is this feature available on this machine
* @name: Name to use in "schemata" file
* @num_closid: Number of CLOSIDs available
* @cache_level: Which cache level defines scope of this resource
* @default_ctrl: Specifies default cache cbm or memory B/W percent.
* @msr_base: Base MSR address for CBMs
* @data_width: Character width of data when displaying
* @domains: All domains for this resource
* @cache: Cache allocation related data
*/
struct rdt_resource {
bool enabled;
bool capable;
char *name;
int num_closid;
int cbm_len;
int min_cbm_bits;
int cache_level;
u32 default_ctrl;
unsigned int msr_base;
int data_width;
struct list_head domains;
int msr_base;
int cache_level;
int cbm_idx_multi;
int cbm_idx_offset;
struct rdt_cache cache;
};
/**

88
arch/x86/kernel/cpu/intel_rdt.c
View File

@ -37,56 +37,64 @@ DEFINE_MUTEX(rdtgroup_mutex);
DEFINE_PER_CPU_READ_MOSTLY(int, cpu_closid);
#define domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].domains)
/*
* Used to store the max resource name width and max resource data width
* to display the schemata in a tabular format
*/
int max_name_width, max_data_width;
#define domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].domains)
struct rdt_resource rdt_resources_all[] = {
{
.name = "L3",
.domains = domain_init(RDT_RESOURCE_L3),
.msr_base = IA32_L3_CBM_BASE,
.min_cbm_bits = 1,
.cache_level = 3,
.cbm_idx_multi = 1,
.cbm_idx_offset = 0
.name = "L3",
.domains = domain_init(RDT_RESOURCE_L3),
.msr_base = IA32_L3_CBM_BASE,
.cache_level = 3,
.cache = {
.min_cbm_bits = 1,
.cbm_idx_mult = 1,
.cbm_idx_offset = 0,
},
},
{
.name = "L3DATA",
.domains = domain_init(RDT_RESOURCE_L3DATA),
.msr_base = IA32_L3_CBM_BASE,
.min_cbm_bits = 1,
.cache_level = 3,
.cbm_idx_multi = 2,
.cbm_idx_offset = 0
.name = "L3DATA",
.domains = domain_init(RDT_RESOURCE_L3DATA),
.msr_base = IA32_L3_CBM_BASE,
.cache_level = 3,
.cache = {
.min_cbm_bits = 1,
.cbm_idx_mult = 2,
.cbm_idx_offset = 0,
},
},
{
.name = "L3CODE",
.domains = domain_init(RDT_RESOURCE_L3CODE),
.msr_base = IA32_L3_CBM_BASE,
.min_cbm_bits = 1,
.cache_level = 3,
.cbm_idx_multi = 2,
.cbm_idx_offset = 1
.name = "L3CODE",
.domains = domain_init(RDT_RESOURCE_L3CODE),
.msr_base = IA32_L3_CBM_BASE,
.cache_level = 3,
.cache = {
.min_cbm_bits = 1,
.cbm_idx_mult = 2,
.cbm_idx_offset = 1,
},
},
{
.name = "L2",
.domains = domain_init(RDT_RESOURCE_L2),
.msr_base = IA32_L2_CBM_BASE,
.min_cbm_bits = 1,
.cache_level = 2,
.cbm_idx_multi = 1,
.cbm_idx_offset = 0
.name = "L2",
.domains = domain_init(RDT_RESOURCE_L2),
.msr_base = IA32_L2_CBM_BASE,
.cache_level = 2,
.cache = {
.min_cbm_bits = 1,
.cbm_idx_mult = 1,
.cbm_idx_offset = 0,
},
},
};
static int cbm_idx(struct rdt_resource *r, int closid)
static unsigned int cbm_idx(struct rdt_resource *r, unsigned int closid)
{
return closid * r->cbm_idx_multi + r->cbm_idx_offset;
return closid * r->cache.cbm_idx_mult + r->cache.cbm_idx_offset;
}
/*
@ -124,9 +132,9 @@ static inline bool cache_alloc_hsw_probe(void)
return false;
r->num_closid = 4;
r->cbm_len = 20;
r->default_ctrl = max_cbm;
r->min_cbm_bits = 2;
r->cache.cbm_len = 20;
r->cache.min_cbm_bits = 2;
r->capable = true;
r->enabled = true;
@ -144,9 +152,9 @@ static void rdt_get_cache_config(int idx, struct rdt_resource *r)
cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full);
r->num_closid = edx.split.cos_max + 1;
r->cbm_len = eax.split.cbm_len + 1;
r->cache.cbm_len = eax.split.cbm_len + 1;
r->default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1;
r->data_width = (r->cbm_len + 3) / 4;
r->data_width = (r->cache.cbm_len + 3) / 4;
r->capable = true;
r->enabled = true;
}
@ -157,9 +165,9 @@ static void rdt_get_cdp_l3_config(int type)
struct rdt_resource *r = &rdt_resources_all[type];
r->num_closid = r_l3->num_closid / 2;
r->cbm_len = r_l3->cbm_len;
r->cache.cbm_len = r_l3->cache.cbm_len;
r->default_ctrl = r_l3->default_ctrl;
r->data_width = (r->cbm_len + 3) / 4;
r->data_width = (r->cache.cbm_len + 3) / 4;
r->capable = true;
/*
* By default, CDP is disabled. CDP can be enabled by mount parameter
@ -200,7 +208,7 @@ void rdt_ctrl_update(void *arg)
found:
for (i = m->low; i < m->high; i++) {
int idx = cbm_idx(r, i);
unsigned int idx = cbm_idx(r, i);
wrmsrl(r->msr_base + idx, d->ctrl_val[i]);
}
@ -282,7 +290,7 @@ static void domain_add_cpu(int cpu, struct rdt_resource *r)
}
for (i = 0; i < r->num_closid; i++) {
int idx = cbm_idx(r, i);
unsigned int idx = cbm_idx(r, i);
d->ctrl_val[i] = r->default_ctrl;
wrmsrl(r->msr_base + idx, d->ctrl_val[i]);

2
arch/x86/kernel/cpu/intel_rdt_rdtgroup.c
View File

@ -534,7 +534,7 @@ static int rdt_min_cbm_bits_show(struct kernfs_open_file *of,
{
struct rdt_resource *r = of->kn->parent->priv;
seq_printf(seq, "%d\n", r->min_cbm_bits);
seq_printf(seq, "%u\n", r->cache.min_cbm_bits);
return 0;
}

9
arch/x86/kernel/cpu/intel_rdt_schemata.c
View File

@ -37,17 +37,18 @@
static bool cbm_validate(unsigned long var, struct rdt_resource *r)
{
unsigned long first_bit, zero_bit;
unsigned int cbm_len = r->cache.cbm_len;
if (var == 0 || var > r->default_ctrl)
return false;
first_bit = find_first_bit(&var, r->cbm_len);
zero_bit = find_next_zero_bit(&var, r->cbm_len, first_bit);
first_bit = find_first_bit(&var, cbm_len);
zero_bit = find_next_zero_bit(&var, cbm_len, first_bit);
if (find_next_bit(&var, r->cbm_len, zero_bit) < r->cbm_len)
if (find_next_bit(&var, cbm_len, zero_bit) < cbm_len)
return false;
if ((zero_bit - first_bit) < r->min_cbm_bits)
if ((zero_bit - first_bit) < r->cache.min_cbm_bits)
return false;
return true;
}