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powerpc/8xx: Better readibility of ERRATA CPU6 handling 

This patch hiddes that SPR address needed for CPU6 ERRATA handling in the macro.
Then we don't have to worry about this address directly in the code.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
LEROY Christophe 2014-09-19 10:36:09 +02:00 committed by Scott Wood
parent 959d6173b5
commit d3e40262e7
1 changed files with 16 additions and 13 deletions
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29
arch/powerpc/kernel/head_8xx.S
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@ -33,12 +33,19 @@
/* Macro to make the code more readable. */ /* Macro to make the code more readable. */
#ifdef CONFIG_8xx_CPU6 #ifdef CONFIG_8xx_CPU6
#define DO_8xx_CPU6(val, reg) \ #define SPRN_MI_TWC_ADDR 0x2b80
li reg, val; \ #define SPRN_MI_RPN_ADDR 0x2d80
stw reg, 12(r0); \ #define SPRN_MD_TWC_ADDR 0x3b80
lwz reg, 12(r0); #define SPRN_MD_RPN_ADDR 0x3d80
#define MTSPR_CPU6(spr, reg, treg) \
li treg, spr##_ADDR; \
stw treg, 12(r0); \
lwz treg, 12(r0); \
mtspr spr, reg
#else #else
#define DO_8xx_CPU6(val, reg) #define MTSPR_CPU6(spr, reg, treg) \
mtspr spr, reg
#endif #endif
/* /*
@ -336,8 +343,7 @@ InstructionTLBMiss:
* for this "segment." * for this "segment."
*/ */
ori r11,r11,1 /* Set valid bit */ ori r11,r11,1 /* Set valid bit */
DO_8xx_CPU6(0x2b80, r3) MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */
mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
mfspr r11, SPRN_SRR0 /* Get effective address of fault */ mfspr r11, SPRN_SRR0 /* Get effective address of fault */
/* Extract level 2 index */ /* Extract level 2 index */
rlwinm r11, r11, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 rlwinm r11, r11, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
@ -356,8 +362,7 @@ InstructionTLBMiss:
*/ */
li r11, RPN_PATTERN li r11, RPN_PATTERN
rlwimi r10, r11, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */ rlwimi r10, r11, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */
DO_8xx_CPU6(0x2d80, r3) MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */
mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
/* Restore registers */ /* Restore registers */
#ifdef CONFIG_8xx_CPU6 #ifdef CONFIG_8xx_CPU6
@ -426,8 +431,7 @@ DataStoreTLBMiss:
* It is bit 25 in the Linux PTE and bit 30 in the TWC * It is bit 25 in the Linux PTE and bit 30 in the TWC
*/ */
rlwimi r11, r10, 32-5, 30, 30 rlwimi r11, r10, 32-5, 30, 30
DO_8xx_CPU6(0x3b80, r3) MTSPR_CPU6(SPRN_MD_TWC, r11, r3)
mtspr SPRN_MD_TWC, r11
/* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set. /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
* We also need to know if the insn is a load/store, so: * We also need to know if the insn is a load/store, so:
@ -460,8 +464,7 @@ DataStoreTLBMiss:
*/ */
2: li r11, RPN_PATTERN 2: li r11, RPN_PATTERN
rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
DO_8xx_CPU6(0x3d80, r3) MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */
mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
/* Restore registers */ /* Restore registers */
#ifdef CONFIG_8xx_CPU6 #ifdef CONFIG_8xx_CPU6