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drm/amd/powerplay: add CZ profile support
Support the profiling modes for sclk. v2: delete profileing mode for mclk. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Tested-and-Reviewed-by Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1312,33 +1312,111 @@ static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
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return 0;
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return 0;
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}
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}
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static int cz_phm_force_dpm_sclk(struct pp_hwmgr *hwmgr, uint32_t sclk)
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{
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_SetSclkSoftMin,
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cz_get_sclk_level(hwmgr,
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sclk,
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PPSMC_MSG_SetSclkSoftMin));
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_SetSclkSoftMax,
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cz_get_sclk_level(hwmgr,
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sclk,
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PPSMC_MSG_SetSclkSoftMax));
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return 0;
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}
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static int cz_get_profiling_clk(struct pp_hwmgr *hwmgr, uint32_t *sclk)
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{
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struct phm_clock_voltage_dependency_table *table =
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hwmgr->dyn_state.vddc_dependency_on_sclk;
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int32_t tmp_sclk;
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int32_t count;
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tmp_sclk = table->entries[table->count-1].clk * 70 / 100;
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for (count = table->count-1; count >= 0; count--) {
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if (tmp_sclk >= table->entries[count].clk) {
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tmp_sclk = table->entries[count].clk;
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*sclk = tmp_sclk;
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break;
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}
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}
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if (count < 0)
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*sclk = table->entries[0].clk;
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return 0;
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}
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static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
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static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
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enum amd_dpm_forced_level level)
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enum amd_dpm_forced_level level)
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{
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{
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uint32_t sclk = 0;
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int ret = 0;
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int ret = 0;
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uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
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AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
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AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
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if (level == hwmgr->dpm_level)
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return ret;
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if (!(hwmgr->dpm_level & profile_mode_mask)) {
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/* enter profile mode, save current level, disable gfx cg*/
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if (level & profile_mode_mask) {
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hwmgr->saved_dpm_level = hwmgr->dpm_level;
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cgs_set_clockgating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_CG_STATE_UNGATE);
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}
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} else {
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/* exit profile mode, restore level, enable gfx cg*/
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if (!(level & profile_mode_mask)) {
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if (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
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level = hwmgr->saved_dpm_level;
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cgs_set_clockgating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_CG_STATE_GATE);
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}
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}
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switch (level) {
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switch (level) {
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case AMD_DPM_FORCED_LEVEL_HIGH:
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case AMD_DPM_FORCED_LEVEL_HIGH:
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case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
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ret = cz_phm_force_dpm_highest(hwmgr);
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ret = cz_phm_force_dpm_highest(hwmgr);
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if (ret)
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if (ret)
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return ret;
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return ret;
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hwmgr->dpm_level = level;
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break;
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break;
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case AMD_DPM_FORCED_LEVEL_LOW:
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case AMD_DPM_FORCED_LEVEL_LOW:
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case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
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ret = cz_phm_force_dpm_lowest(hwmgr);
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ret = cz_phm_force_dpm_lowest(hwmgr);
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if (ret)
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if (ret)
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return ret;
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return ret;
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hwmgr->dpm_level = level;
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break;
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break;
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case AMD_DPM_FORCED_LEVEL_AUTO:
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case AMD_DPM_FORCED_LEVEL_AUTO:
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ret = cz_phm_unforce_dpm_levels(hwmgr);
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ret = cz_phm_unforce_dpm_levels(hwmgr);
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if (ret)
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if (ret)
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return ret;
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return ret;
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hwmgr->dpm_level = level;
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break;
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break;
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case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
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ret = cz_get_profiling_clk(hwmgr, &sclk);
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if (ret)
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return ret;
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hwmgr->dpm_level = level;
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cz_phm_force_dpm_sclk(hwmgr, sclk);
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break;
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case AMD_DPM_FORCED_LEVEL_MANUAL:
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hwmgr->dpm_level = level;
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break;
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case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
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default:
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default:
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break;
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break;
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}
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}
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hwmgr->dpm_level = level;
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return ret;
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return ret;
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}
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}
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