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ARM: dts: mx6qdl: Add CAAM device node
Add CAAM device node to the i.MX6 device tree. Signed-off-by: Victoria Milhoan <vicki.milhoan@freescale.com> Tested-by: Horia Geantă <horia.geanta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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@ -836,10 +836,31 @@ aips-bus@02100000 { /* AIPS2 */
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reg = <0x02100000 0x100000>;
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reg = <0x02100000 0x100000>;
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ranges;
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ranges;
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caam@02100000 {
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crypto: caam@2100000 {
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reg = <0x02100000 0x40000>;
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compatible = "fsl,sec-v4.0";
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interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
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fsl,sec-era = <4>;
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<0 106 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x2100000 0x10000>;
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ranges = <0 0x2100000 0x10000>;
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interrupt-parent = <&intc>;
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clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
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<&clks IMX6QDL_CLK_CAAM_ACLK>,
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<&clks IMX6QDL_CLK_CAAM_IPG>,
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<&clks IMX6QDL_CLK_EIM_SLOW>;
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clock-names = "mem", "aclk", "ipg", "emi_slow";
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sec_jr0: jr0@1000 {
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compatible = "fsl,sec-v4.0-job-ring";
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reg = <0x1000 0x1000>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr1: jr1@2000 {
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compatible = "fsl,sec-v4.0-job-ring";
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reg = <0x2000 0x1000>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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};
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aipstz@0217c000 { /* AIPSTZ2 */
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aipstz@0217c000 { /* AIPSTZ2 */
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