mirror of https://gitee.com/openkylin/linux.git
rtc: snvs: use syscon to access register
snvs included rtc, on/off key, power-off module change to syscon to access register Signed-off-by: Frank Li <Frank.Li@freescale.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Frank Li
Shawn Guo
parent
20c305f660
commit
d482893b1c
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@ -18,6 +18,10 @@
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#include <linux/platform_device.h>
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#include <linux/rtc.h>
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#include <linux/clk.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#define SNVS_LPREGISTER_OFFSET 0x34
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/* These register offsets are relative to LP (Low Power) range */
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#define SNVS_LPCR 0x04
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@ -37,31 +41,36 @@
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struct snvs_rtc_data {
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struct rtc_device *rtc;
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void __iomem *ioaddr;
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struct regmap *regmap;
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int offset;
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int irq;
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spinlock_t lock;
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struct clk *clk;
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};
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static u32 rtc_read_lp_counter(void __iomem *ioaddr)
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static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
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{
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u64 read1, read2;
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u32 val;
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do {
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read1 = readl(ioaddr + SNVS_LPSRTCMR);
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regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &val);
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read1 = val;
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read1 <<= 32;
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read1 |= readl(ioaddr + SNVS_LPSRTCLR);
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regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &val);
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read1 |= val;
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read2 = readl(ioaddr + SNVS_LPSRTCMR);
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regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &val);
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read2 = val;
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read2 <<= 32;
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read2 |= readl(ioaddr + SNVS_LPSRTCLR);
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regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &val);
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read2 |= val;
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} while (read1 != read2);
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/* Convert 47-bit counter to 32-bit raw second count */
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return (u32) (read1 >> CNTR_TO_SECS_SH);
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}
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static void rtc_write_sync_lp(void __iomem *ioaddr)
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static void rtc_write_sync_lp(struct snvs_rtc_data *data)
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{
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u32 count1, count2, count3;
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int i;
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@ -69,15 +78,15 @@ static void rtc_write_sync_lp(void __iomem *ioaddr)
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/* Wait for 3 CKIL cycles */
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for (i = 0; i < 3; i++) {
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do {
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count1 = readl(ioaddr + SNVS_LPSRTCLR);
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count2 = readl(ioaddr + SNVS_LPSRTCLR);
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regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
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regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count2);
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} while (count1 != count2);
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/* Now wait until counter value changes */
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do {
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do {
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count2 = readl(ioaddr + SNVS_LPSRTCLR);
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count3 = readl(ioaddr + SNVS_LPSRTCLR);
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regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count2);
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regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count3);
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} while (count2 != count3);
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} while (count3 == count1);
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}
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@ -85,23 +94,14 @@ static void rtc_write_sync_lp(void __iomem *ioaddr)
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static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
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{
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unsigned long flags;
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int timeout = 1000;
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u32 lpcr;
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spin_lock_irqsave(&data->lock, flags);
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lpcr = readl(data->ioaddr + SNVS_LPCR);
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if (enable)
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lpcr |= SNVS_LPCR_SRTC_ENV;
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else
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lpcr &= ~SNVS_LPCR_SRTC_ENV;
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writel(lpcr, data->ioaddr + SNVS_LPCR);
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spin_unlock_irqrestore(&data->lock, flags);
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regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
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enable ? SNVS_LPCR_SRTC_ENV : 0);
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while (--timeout) {
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lpcr = readl(data->ioaddr + SNVS_LPCR);
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regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);
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if (enable) {
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if (lpcr & SNVS_LPCR_SRTC_ENV)
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@ -121,7 +121,7 @@ static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
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static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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unsigned long time = rtc_read_lp_counter(data->ioaddr);
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unsigned long time = rtc_read_lp_counter(data);
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rtc_time_to_tm(time, tm);
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@ -139,8 +139,8 @@ static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
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snvs_rtc_enable(data, false);
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/* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
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writel(time << CNTR_TO_SECS_SH, data->ioaddr + SNVS_LPSRTCLR);
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writel(time >> (32 - CNTR_TO_SECS_SH), data->ioaddr + SNVS_LPSRTCMR);
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regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
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regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));
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/* Enable RTC again */
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snvs_rtc_enable(data, true);
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@ -153,10 +153,10 @@ static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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u32 lptar, lpsr;
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lptar = readl(data->ioaddr + SNVS_LPTAR);
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regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
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rtc_time_to_tm(lptar, &alrm->time);
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lpsr = readl(data->ioaddr + SNVS_LPSR);
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regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
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alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
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return 0;
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@ -165,21 +165,12 @@ static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
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{
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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u32 lpcr;
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unsigned long flags;
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spin_lock_irqsave(&data->lock, flags);
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regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
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(SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN),
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enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0);
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lpcr = readl(data->ioaddr + SNVS_LPCR);
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if (enable)
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lpcr |= (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN);
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else
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lpcr &= ~(SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN);
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writel(lpcr, data->ioaddr + SNVS_LPCR);
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spin_unlock_irqrestore(&data->lock, flags);
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rtc_write_sync_lp(data->ioaddr);
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rtc_write_sync_lp(data);
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return 0;
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}
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@ -189,24 +180,14 @@ static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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struct rtc_time *alrm_tm = &alrm->time;
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unsigned long time;
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unsigned long flags;
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u32 lpcr;
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rtc_tm_to_time(alrm_tm, &time);
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spin_lock_irqsave(&data->lock, flags);
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/* Have to clear LPTA_EN before programming new alarm time in LPTAR */
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lpcr = readl(data->ioaddr + SNVS_LPCR);
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lpcr &= ~SNVS_LPCR_LPTA_EN;
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writel(lpcr, data->ioaddr + SNVS_LPCR);
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spin_unlock_irqrestore(&data->lock, flags);
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writel(time, data->ioaddr + SNVS_LPTAR);
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regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
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regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);
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/* Clear alarm interrupt status bit */
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writel(SNVS_LPSR_LPTA, data->ioaddr + SNVS_LPSR);
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regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);
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return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
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}
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@ -226,7 +207,7 @@ static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
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u32 lpsr;
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u32 events = 0;
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lpsr = readl(data->ioaddr + SNVS_LPSR);
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regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
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if (lpsr & SNVS_LPSR_LPTA) {
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events |= (RTC_AF | RTC_IRQF);
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@ -238,25 +219,48 @@ static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
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}
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/* clear interrupt status */
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writel(lpsr, data->ioaddr + SNVS_LPSR);
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regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);
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return events ? IRQ_HANDLED : IRQ_NONE;
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}
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static const struct regmap_config snvs_rtc_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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};
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static int snvs_rtc_probe(struct platform_device *pdev)
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{
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struct snvs_rtc_data *data;
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struct resource *res;
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int ret;
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void __iomem *mmio;
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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data->ioaddr = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(data->ioaddr))
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return PTR_ERR(data->ioaddr);
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data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
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if (IS_ERR(data->regmap)) {
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dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mmio = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(mmio))
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return PTR_ERR(mmio);
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data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
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} else {
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data->offset = SNVS_LPREGISTER_OFFSET;
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of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
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}
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if (!data->regmap) {
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dev_err(&pdev->dev, "Can't find snvs syscon\n");
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return -ENODEV;
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}
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data->irq = platform_get_irq(pdev, 0);
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if (data->irq < 0)
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@ -276,13 +280,11 @@ static int snvs_rtc_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, data);
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spin_lock_init(&data->lock);
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/* Initialize glitch detect */
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writel(SNVS_LPPGDR_INIT, data->ioaddr + SNVS_LPPGDR);
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regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);
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/* Clear interrupt status */
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writel(0xffffffff, data->ioaddr + SNVS_LPSR);
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regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);
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/* Enable RTC */
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snvs_rtc_enable(data, true);
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