From a6a4abf8efeeadb762b5160f128f30c3c5c8e4ff Mon Sep 17 00:00:00 2001 From: Daniele Alessandrelli Date: Fri, 17 Jul 2020 10:04:10 +0100 Subject: [PATCH 01/38] arm64: Add config for Keem Bay SoC Add ARCH_KEEMBAY configuration option to support Intel Movidius SoC code-named Keem Bay. Link: https://lore.kernel.org/r/20200717090414.313530-2-daniele.alessandrelli@linux.intel.com Reviewed-by: Dinh Nguyen Signed-off-by: Daniele Alessandrelli Signed-off-by: Arnd Bergmann --- arch/arm64/Kconfig.platforms | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 8dd05b2a925c..95c1b9042009 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -121,6 +121,11 @@ config ARCH_HISI help This enables support for Hisilicon ARMv8 SoC family +config ARCH_KEEMBAY + bool "Keem Bay SoC" + help + This enables support for Intel Movidius SoC code-named Keem Bay. + config ARCH_MEDIATEK bool "MediaTek SoC Family" select ARM_GIC From 37de951b3656eb0421065695409e7dbeaccee039 Mon Sep 17 00:00:00 2001 From: Daniele Alessandrelli Date: Fri, 17 Jul 2020 10:04:11 +0100 Subject: [PATCH 02/38] dt-bindings: arm: Add Keem Bay bindings Document Intel Movidius SoC code-named Keem Bay, along with the Keem Bay EVM board. Link: https://lore.kernel.org/r/20200717090414.313530-3-daniele.alessandrelli@linux.intel.com Reviewed-by: Dinh Nguyen Reviewed-by: Rob Herring Signed-off-by: Daniele Alessandrelli Signed-off-by: Arnd Bergmann --- .../bindings/arm/intel,keembay.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/intel,keembay.yaml diff --git a/Documentation/devicetree/bindings/arm/intel,keembay.yaml b/Documentation/devicetree/bindings/arm/intel,keembay.yaml new file mode 100644 index 000000000000..4d925785f504 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/intel,keembay.yaml @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/intel,keembay.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Keem Bay platform device tree bindings + +maintainers: + - Paul J. Murphy + - Daniele Alessandrelli + +properties: + compatible: + items: + - enum: + - intel,keembay-evm + - const: intel,keembay +... From c98459cf6d8d26ff0989eb5aae5a4b9f261d58c6 Mon Sep 17 00:00:00 2001 From: Daniele Alessandrelli Date: Fri, 17 Jul 2020 10:04:12 +0100 Subject: [PATCH 03/38] MAINTAINERS: Add maintainers for Keem Bay SoC Add maintainers for the new Intel Movidius SoC code-named Keem Bay. Link: https://lore.kernel.org/r/20200717090414.313530-4-daniele.alessandrelli@linux.intel.com Reviewed-by: Dinh Nguyen Signed-off-by: Daniele Alessandrelli Signed-off-by: Arnd Bergmann --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7b5ffd646c6b..fd46dfc88c50 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1954,6 +1954,12 @@ F: drivers/irqchip/irq-ixp4xx.c F: include/linux/irqchip/irq-ixp4xx.h F: include/linux/platform_data/timer-ixp4xx.h +ARM/INTEL KEEMBAY ARCHITECTURE +M: Paul J. Murphy +M: Daniele Alessandrelli +S: Maintained +F: Documentation/devicetree/bindings/arm/intel,keembay.yaml + ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT M: Jonathan Cameron L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) From 0a6e92f26784b8c6a9d24c26da7278a7362531ee Mon Sep 17 00:00:00 2001 From: Daniele Alessandrelli Date: Fri, 17 Jul 2020 10:04:13 +0100 Subject: [PATCH 04/38] arm64: dts: keembay: Add device tree for Keem Bay SoC Add initial device tree for Intel Movidius SoC code-named Keem Bay. This initial DT includes nodes for Cortex-A53 cores, UARTs, GIC, PSCI, and PMU. Link: https://lore.kernel.org/r/20200717090414.313530-5-daniele.alessandrelli@linux.intel.com Reviewed-by: Dinh Nguyen Signed-off-by: Daniele Alessandrelli Signed-off-by: Arnd Bergmann --- MAINTAINERS | 1 + arch/arm64/boot/dts/intel/keembay-soc.dtsi | 123 +++++++++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/keembay-soc.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index fd46dfc88c50..5bcd1c412f0b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1959,6 +1959,7 @@ M: Paul J. Murphy M: Daniele Alessandrelli S: Maintained F: Documentation/devicetree/bindings/arm/intel,keembay.yaml +F: arch/arm64/boot/dts/intel/keembay-soc.dtsi ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT M: Jonathan Cameron diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi new file mode 100644 index 000000000000..781761d2942b --- /dev/null +++ b/arch/arm64/boot/dts/intel/keembay-soc.dtsi @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) 2020, Intel Corporation. + * + * Device tree describing Keem Bay SoC. + */ + +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + gic: interrupt-controller@20500000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0 0x20500000 0x0 0x20000>, /* GICD */ + <0x0 0x20580000 0x0 0x80000>; /* GICR */ + /* VGIC maintenance interrupt */ + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + /* Secure, non-secure, virtual, and hypervisor */ + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: serial@20150000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20150000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@20160000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20160000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@20170000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20170000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@20180000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20180000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + }; +}; From d846abff949d346ffc0fe31d492c2af00ea40e2e Mon Sep 17 00:00:00 2001 From: Daniele Alessandrelli Date: Fri, 17 Jul 2020 10:04:14 +0100 Subject: [PATCH 05/38] arm64: dts: keembay: Add device tree for Keem Bay EVM board Add initial device tree for Keem Bay EVM board. With this minimal device tree the board boots fine using an initramfs image. Link: https://lore.kernel.org/r/20200717090414.313530-6-daniele.alessandrelli@linux.intel.com Reviewed-by: Dinh Nguyen Signed-off-by: Daniele Alessandrelli Signed-off-by: Arnd Bergmann --- MAINTAINERS | 1 + arch/arm64/boot/dts/intel/Makefile | 1 + arch/arm64/boot/dts/intel/keembay-evm.dts | 37 +++++++++++++++++++++++ 3 files changed, 39 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/keembay-evm.dts diff --git a/MAINTAINERS b/MAINTAINERS index 5bcd1c412f0b..f139d9594564 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1959,6 +1959,7 @@ M: Paul J. Murphy M: Daniele Alessandrelli S: Maintained F: Documentation/devicetree/bindings/arm/intel,keembay.yaml +F: arch/arm64/boot/dts/intel/keembay-evm.dts F: arch/arm64/boot/dts/intel/keembay-soc.dtsi ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index 40cb16e8c814..296eceec4276 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_nand.dtb +dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/keembay-evm.dts b/arch/arm64/boot/dts/intel/keembay-evm.dts new file mode 100644 index 000000000000..466c85363a29 --- /dev/null +++ b/arch/arm64/boot/dts/intel/keembay-evm.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) 2020, Intel Corporation + * + * Device tree describing Keem Bay EVM board. + */ + +/dts-v1/; + +#include "keembay-soc.dtsi" + +/ { + model = "Keem Bay EVM"; + compatible = "intel,keembay-evm", "intel,keembay"; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + /* 2GB of DDR memory. */ + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + +}; + +&uart3 { + status = "okay"; +}; From 85032207c86dcb6e13a3afd0650c44ecfc6df4c6 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Mon, 15 Jun 2020 15:32:33 +0200 Subject: [PATCH 06/38] dt-bindings: arm: sparx5: Add documentation for Microchip Sparx5 SoC This adds the main Sparx5 SoC DT documentation file, with information abut the supported board types. Link: https://lore.kernel.org/r/20200615133242.24911-2-lars.povlsen@microchip.com Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen Reviewed-by: Rob Herring Signed-off-by: Arnd Bergmann --- .../bindings/arm/microchip,sparx5.yaml | 65 +++++++++++++++++++ .../devicetree/bindings/mfd/syscon.yaml | 1 + 2 files changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/microchip,sparx5.yaml diff --git a/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml b/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml new file mode 100644 index 000000000000..ecf6fa12e6ad --- /dev/null +++ b/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Sparx5 Boards Device Tree Bindings + +maintainers: + - Lars Povlsen + +description: |+ + The Microchip Sparx5 SoC is a ARMv8-based used in a family of + gigabit TSN-capable gigabit switches. + + The SparX-5 Ethernet switch family provides a rich set of switching + features such as advanced TCAM-based VLAN and QoS processing + enabling delivery of differentiated services, and security through + TCAM-based frame processing using versatile content aware processor + (VCAP) + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: The Sparx5 pcb125 board is a modular board, + which has both spi-nor and eMMC storage. The modular design + allows for connection of different network ports. + items: + - const: microchip,sparx5-pcb125 + - const: microchip,sparx5 + + - description: The Sparx5 pcb134 is a pizzabox form factor + gigabit switch with 20 SFP ports. It features spi-nor and + either spi-nand or eMMC storage (mount option). + items: + - const: microchip,sparx5-pcb134 + - const: microchip,sparx5 + + - description: The Sparx5 pcb135 is a pizzabox form factor + gigabit switch with 48+4 Cu ports. It features spi-nor and + either spi-nand or eMMC storage (mount option). + items: + - const: microchip,sparx5-pcb135 + - const: microchip,sparx5 + + axi@600000000: + type: object + description: the root node in the Sparx5 platforms must contain + an axi bus child node. They are always at physical address + 0x600000000 in all the Sparx5 variants. + properties: + compatible: + items: + - const: simple-bus + + required: + - compatible + +required: + - compatible + - axi@600000000 + +... diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 19bdaf781853..f3fba860d3cc 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -38,6 +38,7 @@ properties: - allwinner,sun8i-h3-system-controller - allwinner,sun8i-v3s-system-controller - allwinner,sun50i-a64-system-controller + - microchip,sparx5-cpu-syscon - const: syscon From 31a91c87a42bf3f7261e5752db5784fa43fbced5 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Mon, 15 Jun 2020 15:32:34 +0200 Subject: [PATCH 07/38] arm64: sparx5: Add support for Microchip 2xA53 SoC This adds support for the Microchip Sparx5 ARMv8-based SoC family of TSN-capable gigabit switches. Link: https://lore.kernel.org/r/20200615133242.24911-3-lars.povlsen@microchip.com Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen Signed-off-by: Arnd Bergmann --- MAINTAINERS | 8 ++++++++ arch/arm64/Kconfig.platforms | 14 ++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f139d9594564..104972340822 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2119,6 +2119,14 @@ X: drivers/net/wireless/atmel/ N: at91 N: atmel +ARM/Microchip Sparx5 SoC support +M: Lars Povlsen +M: Steen Hegelund +M: Microchip Linux Driver Support +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +N: sparx5 + ARM/MIOA701 MACHINE SUPPORT M: Robert Jarzmik L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 95c1b9042009..fd9f45a52879 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -89,6 +89,20 @@ config ARCH_EXYNOS help This enables support for ARMv8 based Samsung Exynos SoC family. +config ARCH_SPARX5 + bool "ARMv8 based Microchip Sparx5 SoC family" + select PINCTRL + select DW_APB_TIMER_OF + help + This enables support for the Microchip Sparx5 ARMv8-based + SoC family of TSN-capable gigabit switches. + + The SparX-5 Ethernet switch family provides a rich set of + switching features such as advanced TCAM-based VLAN and QoS + processing enabling delivery of differentiated services, and + security through TCAM-based frame processing using versatile + content aware processor (VCAP). + config ARCH_K3 bool "Texas Instruments Inc. K3 multicore SoC architecture" select PM_GENERIC_DOMAINS if PM From 6694aee00a4b478d2dd82837f39b5dc9cbedfbcf Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Mon, 15 Jun 2020 15:32:35 +0200 Subject: [PATCH 08/38] arm64: dts: sparx5: Add basic cpu support This adds the basic DT structure for the Microchip Sparx5 SoC, and the reference boards, pcb125, pcb134 and pcb135. The two latter have a NAND vs a eMMC centric variant (as a mount option). Link: https://lore.kernel.org/r/20200615133242.24911-4-lars.povlsen@microchip.com Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen Signed-off-by: Arnd Bergmann --- MAINTAINERS | 1 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/microchip/Makefile | 4 + arch/arm64/boot/dts/microchip/sparx5.dtsi | 142 ++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb125.dts | 17 +++ .../boot/dts/microchip/sparx5_pcb134.dts | 17 +++ .../dts/microchip/sparx5_pcb134_board.dtsi | 10 ++ .../boot/dts/microchip/sparx5_pcb134_emmc.dts | 17 +++ .../boot/dts/microchip/sparx5_pcb135.dts | 17 +++ .../dts/microchip/sparx5_pcb135_board.dtsi | 10 ++ .../boot/dts/microchip/sparx5_pcb135_emmc.dts | 17 +++ .../boot/dts/microchip/sparx5_pcb_common.dtsi | 15 ++ 12 files changed, 268 insertions(+) create mode 100644 arch/arm64/boot/dts/microchip/Makefile create mode 100644 arch/arm64/boot/dts/microchip/sparx5.dtsi create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb125.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 104972340822..fc6b50723c22 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2125,6 +2125,7 @@ M: Steen Hegelund M: Microchip Linux Driver Support L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported +F: arch/arm64/boot/dts/microchip/ N: sparx5 ARM/MIOA701 MACHINE SUPPORT diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index f19b762c008d..9680a7f20c30 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -17,6 +17,7 @@ subdir-y += intel subdir-y += lg subdir-y += marvell subdir-y += mediatek +subdir-y += microchip subdir-y += nvidia subdir-y += qcom subdir-y += realtek diff --git a/arch/arm64/boot/dts/microchip/Makefile b/arch/arm64/boot/dts/microchip/Makefile new file mode 100644 index 000000000000..c6e0313eea0f --- /dev/null +++ b/arch/arm64/boot/dts/microchip/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi new file mode 100644 index 000000000000..4a54b7d03916 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +#include +#include + +/ { + compatible = "microchip,sparx5"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + clocks: clocks { + #address-cells = <2>; + #size-cells = <1>; + ranges; + ahb_clk: ahb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + sys_clk: sys-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <625000000>; + }; + }; + + axi: axi@600000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + gic: interrupt-controller@600300000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + reg = <0x6 0x00300000 0x10000>, /* GIC Dist */ + <0x6 0x00340000 0xc0000>, /* GICR */ + <0x6 0x00200000 0x2000>, /* GICC */ + <0x6 0x00210000 0x2000>, /* GICV */ + <0x6 0x00220000 0x2000>; /* GICH */ + interrupts = ; + }; + + uart0: serial@600100000 { + compatible = "ns16550a"; + reg = <0x6 0x00100000 0x20>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + + status = "disabled"; + }; + + uart1: serial@600102000 { + compatible = "ns16550a"; + reg = <0x6 0x00102000 0x20>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + + status = "disabled"; + }; + + timer1: timer@600105000 { + compatible = "snps,dw-apb-timer"; + reg = <0x6 0x00105000 0x1000>; + clocks = <&ahb_clk>; + clock-names = "timer"; + interrupts = ; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts new file mode 100644 index 000000000000..d7f985f7ee02 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb_common.dtsi" + +/ { + model = "Sparx5 PCB125 Reference Board"; + compatible = "microchip,sparx5-pcb125", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts new file mode 100644 index 000000000000..feee4e99ff57 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb134_board.dtsi" + +/ { + model = "Sparx5 PCB134 Reference Board (NAND)"; + compatible = "microchip,sparx5-pcb134", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi new file mode 100644 index 000000000000..005cf6babb9b --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb_common.dtsi" + +/{ +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts new file mode 100644 index 000000000000..10081a66961b --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb134_board.dtsi" + +/ { + model = "Sparx5 PCB134 Reference Board (eMMC enabled)"; + compatible = "microchip,sparx5-pcb134", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts new file mode 100644 index 000000000000..20e409a9be19 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb135_board.dtsi" + +/ { + model = "Sparx5 PCB135 Reference Board (NAND)"; + compatible = "microchip,sparx5-pcb135", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi new file mode 100644 index 000000000000..005cf6babb9b --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb_common.dtsi" + +/{ +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts new file mode 100644 index 000000000000..741f0e12260e --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb135_board.dtsi" + +/ { + model = "Sparx5 PCB135 Reference Board (eMMC enabled)"; + compatible = "microchip,sparx5-pcb135", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi new file mode 100644 index 000000000000..1f99d0db1284 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5.dtsi" + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; From 14bc6703b387cac2a9bec8f8d6bbffea63db43ea Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Mon, 15 Jun 2020 15:32:36 +0200 Subject: [PATCH 09/38] arm64: dts: sparx5: Add pinctrl support This add pinctrl support to the Microchip Sparx5 SoC. Link: https://lore.kernel.org/r/20200615133242.24911-5-lars.povlsen@microchip.com Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 26 +++++++++++++++++++ .../dts/microchip/sparx5_pcb134_board.dtsi | 5 ++++ .../dts/microchip/sparx5_pcb135_board.dtsi | 5 ++++ 3 files changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 4a54b7d03916..baf4176ce1df 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -109,6 +109,8 @@ gic: interrupt-controller@600300000 { }; uart0: serial@600100000 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; compatible = "ns16550a"; reg = <0x6 0x00100000 0x20>; clocks = <&ahb_clk>; @@ -120,6 +122,8 @@ uart0: serial@600100000 { }; uart1: serial@600102000 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; compatible = "ns16550a"; reg = <0x6 0x00102000 0x20>; clocks = <&ahb_clk>; @@ -138,5 +142,27 @@ timer1: timer@600105000 { interrupts = ; }; + gpio: pinctrl@6110101e0 { + compatible = "microchip,sparx5-pinctrl"; + reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 64>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + + uart_pins: uart-pins { + pins = "GPIO_10", "GPIO_11"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_26", "GPIO_27"; + function = "uart2"; + }; + + }; + }; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index 005cf6babb9b..9b2aec400101 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -7,4 +7,9 @@ #include "sparx5_pcb_common.dtsi" /{ + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + priority = <200>; + }; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index 005cf6babb9b..9b2aec400101 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -7,4 +7,9 @@ #include "sparx5_pcb_common.dtsi" /{ + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + priority = <200>; + }; }; From 2ce39f20d0bfa2cae289beaf0ab1aa37fb2b93e6 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Mon, 15 Jun 2020 15:32:38 +0200 Subject: [PATCH 10/38] dt-bindings: clock: sparx5: Add Sparx5 SoC DPLL clock This add the DT bindings documentation for the Sparx5 SoC DPLL clock Link: https://lore.kernel.org/r/20200615133242.24911-7-lars.povlsen@microchip.com Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen Reviewed-by: Rob Herring Signed-off-by: Arnd Bergmann --- .../bindings/clock/microchip,sparx5-dpll.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml diff --git a/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml new file mode 100644 index 000000000000..39559a0a598a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Sparx5 DPLL Clock + +maintainers: + - Lars Povlsen + +description: | + The Sparx5 DPLL clock controller generates and supplies clock to + various peripherals within the SoC. + +properties: + compatible: + const: microchip,sparx5-dpll + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock provider for eMMC: + - | + lcpll_clk: lcpll-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2500000000>; + }; + clks: clock-controller@61110000c { + compatible = "microchip,sparx5-dpll"; + #clock-cells = <1>; + clocks = <&lcpll_clk>; + reg = <0x1110000c 0x24>; + }; + +... From 39c8378a1cdf856a3671b6431f99352b75a07248 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Mon, 15 Jun 2020 15:32:39 +0200 Subject: [PATCH 11/38] dt-bindings: clock: sparx5: Add bindings include file The Sparx5 support 9 different clock outputs. This include file has defines for each supported clock ordinal. Link: https://lore.kernel.org/r/20200615133242.24911-8-lars.povlsen@microchip.com Reviewed-by: Stephen Boyd Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen Reviewed-by: Rob Herring Signed-off-by: Arnd Bergmann --- include/dt-bindings/clock/microchip,sparx5.h | 23 ++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 include/dt-bindings/clock/microchip,sparx5.h diff --git a/include/dt-bindings/clock/microchip,sparx5.h b/include/dt-bindings/clock/microchip,sparx5.h new file mode 100644 index 000000000000..4b04dabacec2 --- /dev/null +++ b/include/dt-bindings/clock/microchip,sparx5.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019 Microchip Inc. + * + * Author: Lars Povlsen + */ + +#ifndef _DT_BINDINGS_CLK_SPARX5_H +#define _DT_BINDINGS_CLK_SPARX5_H + +#define CLK_ID_CORE 0 +#define CLK_ID_DDR 1 +#define CLK_ID_CPU2 2 +#define CLK_ID_ARM2 3 +#define CLK_ID_AUX1 4 +#define CLK_ID_AUX2 5 +#define CLK_ID_AUX3 6 +#define CLK_ID_AUX4 7 +#define CLK_ID_SYNCE 8 + +#define N_CLOCKS 9 + +#endif From e4e06a50b04296d17a4cf098a515fb452106ecf0 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Mon, 15 Jun 2020 15:32:41 +0200 Subject: [PATCH 12/38] arm64: dts: sparx5: Add Sparx5 SoC DPLL clock This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock to misc peripherals, specifically the SDHCI/eMMC controller. Link: https://lore.kernel.org/r/20200615133242.24911-10-lars.povlsen@microchip.com Signed-off-by: Lars Povlsen Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 39 +++++++++++++---------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index baf4176ce1df..161846caf9c9 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -72,20 +72,29 @@ timer { ; }; - clocks: clocks { - #address-cells = <2>; - #size-cells = <1>; - ranges; - ahb_clk: ahb-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - }; - sys_clk: sys-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <625000000>; - }; + lcpll_clk: lcpll-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2500000000>; + }; + + clks: clock-controller@61110000c { + compatible = "microchip,sparx5-dpll"; + #clock-cells = <1>; + clocks = <&lcpll_clk>; + reg = <0x6 0x1110000c 0x24>; + }; + + ahb_clk: ahb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + sys_clk: sys-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <625000000>; }; axi: axi@600000000 { @@ -161,8 +170,6 @@ uart2_pins: uart2-pins { pins = "GPIO_26", "GPIO_27"; function = "uart2"; }; - }; - }; }; From 623910f4b9f5a4db49c8cc4b824c1f32236a6f33 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Mon, 15 Jun 2020 15:32:42 +0200 Subject: [PATCH 13/38] arm64: dts: sparx5: Add i2c devices, i2c muxes This patch adds i2c devices and muxes to the Sparx5 reference boards. Link: https://lore.kernel.org/r/20200615133242.24911-11-lars.povlsen@microchip.com Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 38 +++ .../boot/dts/microchip/sparx5_pcb125.dts | 4 + .../dts/microchip/sparx5_pcb134_board.dtsi | 237 ++++++++++++++++++ .../dts/microchip/sparx5_pcb135_board.dtsi | 77 ++++++ .../boot/dts/microchip/sparx5_pcb_common.dtsi | 4 + 5 files changed, 360 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 161846caf9c9..cf712e80615d 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -170,6 +170,44 @@ uart2_pins: uart2-pins { pins = "GPIO_26", "GPIO_27"; function = "uart2"; }; + + i2c_pins: i2c-pins { + pins = "GPIO_14", "GPIO_15"; + function = "twi"; + }; + + i2c2_pins: i2c2-pins { + pins = "GPIO_28", "GPIO_29"; + function = "twi2"; + }; + }; + + i2c0: i2c@600101000 { + compatible = "snps,designware-i2c"; + status = "disabled"; + pinctrl-0 = <&i2c_pins>; + pinctrl-names = "default"; + reg = <0x6 0x00101000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + i2c-sda-hold-time-ns = <300>; + clock-frequency = <100000>; + clocks = <&ahb_clk>; + }; + + i2c1: i2c@600103000 { + compatible = "snps,designware-i2c"; + status = "disabled"; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + reg = <0x6 0x00103000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + i2c-sda-hold-time-ns = <300>; + clock-frequency = <100000>; + clocks = <&ahb_clk>; }; }; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index d7f985f7ee02..91ee5b6cfc37 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -15,3 +15,7 @@ memory@0 { reg = <0x00000000 0x00000000 0x10000000>; }; }; + +&i2c1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index 9b2aec400101..18a535a04368 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -7,9 +7,246 @@ #include "sparx5_pcb_common.dtsi" /{ + aliases { + i2c0 = &i2c0; + i2c100 = &i2c100; + i2c101 = &i2c101; + i2c102 = &i2c102; + i2c103 = &i2c103; + i2c104 = &i2c104; + i2c105 = &i2c105; + i2c106 = &i2c106; + i2c107 = &i2c107; + i2c108 = &i2c108; + i2c109 = &i2c109; + i2c110 = &i2c110; + i2c111 = &i2c111; + i2c112 = &i2c112; + i2c113 = &i2c113; + i2c114 = &i2c114; + i2c115 = &i2c115; + i2c116 = &i2c116; + i2c117 = &i2c117; + i2c118 = &i2c118; + i2c119 = &i2c119; + }; + gpio-restart { compatible = "gpio-restart"; gpios = <&gpio 37 GPIO_ACTIVE_LOW>; priority = <200>; }; }; + +&gpio { + i2cmux_pins_i: i2cmux-pins-i { + pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19", + "GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35", + "GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57"; + function = "twi_scl_m"; + output-low; + }; + i2cmux_0: i2cmux-0 { + pins = "GPIO_16"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_1: i2cmux-1 { + pins = "GPIO_17"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_2: i2cmux-2 { + pins = "GPIO_18"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_3: i2cmux-3 { + pins = "GPIO_19"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_4: i2cmux-4 { + pins = "GPIO_20"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_5: i2cmux-5 { + pins = "GPIO_22"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_6: i2cmux-6 { + pins = "GPIO_36"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_7: i2cmux-7 { + pins = "GPIO_35"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_8: i2cmux-8 { + pins = "GPIO_50"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_9: i2cmux-9 { + pins = "GPIO_51"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_10: i2cmux-10 { + pins = "GPIO_56"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_11: i2cmux-11 { + pins = "GPIO_57"; + function = "twi_scl_m"; + output-high; + }; +}; + +&axi { + i2c0_imux: i2c0-imux@0 { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c0>; + }; + i2c0_emux: i2c0-emux@0 { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c0>; + }; +}; + +&i2c0_imux { + pinctrl-names = + "i2c100", "i2c101", "i2c102", "i2c103", + "i2c104", "i2c105", "i2c106", "i2c107", + "i2c108", "i2c109", "i2c110", "i2c111", "idle"; + pinctrl-0 = <&i2cmux_0>; + pinctrl-1 = <&i2cmux_1>; + pinctrl-2 = <&i2cmux_2>; + pinctrl-3 = <&i2cmux_3>; + pinctrl-4 = <&i2cmux_4>; + pinctrl-5 = <&i2cmux_5>; + pinctrl-6 = <&i2cmux_6>; + pinctrl-7 = <&i2cmux_7>; + pinctrl-8 = <&i2cmux_8>; + pinctrl-9 = <&i2cmux_9>; + pinctrl-10 = <&i2cmux_10>; + pinctrl-11 = <&i2cmux_11>; + pinctrl-12 = <&i2cmux_pins_i>; + i2c100: i2c_sfp1 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c101: i2c_sfp2 { + reg = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c102: i2c_sfp3 { + reg = <0x2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c103: i2c_sfp4 { + reg = <0x3>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c104: i2c_sfp5 { + reg = <0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c105: i2c_sfp6 { + reg = <0x5>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c106: i2c_sfp7 { + reg = <0x6>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c107: i2c_sfp8 { + reg = <0x7>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c108: i2c_sfp9 { + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c109: i2c_sfp10 { + reg = <0x9>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c110: i2c_sfp11 { + reg = <0xa>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c111: i2c_sfp12 { + reg = <0xb>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&i2c0_emux { + mux-gpios = <&gpio 55 GPIO_ACTIVE_HIGH + &gpio 60 GPIO_ACTIVE_HIGH + &gpio 61 GPIO_ACTIVE_HIGH + &gpio 54 GPIO_ACTIVE_HIGH>; + idle-state = <0x8>; + i2c112: i2c_sfp13 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c113: i2c_sfp14 { + reg = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c114: i2c_sfp15 { + reg = <0x2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c115: i2c_sfp16 { + reg = <0x3>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c116: i2c_sfp17 { + reg = <0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c117: i2c_sfp18 { + reg = <0x5>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c118: i2c_sfp19 { + reg = <0x6>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c119: i2c_sfp20 { + reg = <0x7>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index 9b2aec400101..d71f11a10b3d 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -7,9 +7,86 @@ #include "sparx5_pcb_common.dtsi" /{ + aliases { + i2c0 = &i2c0; + i2c152 = &i2c152; + i2c153 = &i2c153; + i2c154 = &i2c154; + i2c155 = &i2c155; + }; + gpio-restart { compatible = "gpio-restart"; gpios = <&gpio 37 GPIO_ACTIVE_LOW>; priority = <200>; }; }; + +&gpio { + i2cmux_pins_i: i2cmux-pins-i { + pins = "GPIO_35", "GPIO_36", + "GPIO_50", "GPIO_51"; + function = "twi_scl_m"; + output-low; + }; + i2cmux_s29: i2cmux-0 { + pins = "GPIO_35"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_s30: i2cmux-1 { + pins = "GPIO_36"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_s31: i2cmux-2 { + pins = "GPIO_50"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_s32: i2cmux-3 { + pins = "GPIO_51"; + function = "twi_scl_m"; + output-high; + }; +}; + +&axi { + i2c0_imux: i2c0-imux@0 { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c0>; + }; +}; + +&i2c0_imux { + pinctrl-names = + "i2c152", "i2c153", "i2c154", "i2c155", + "idle"; + pinctrl-0 = <&i2cmux_s29>; + pinctrl-1 = <&i2cmux_s30>; + pinctrl-2 = <&i2cmux_s31>; + pinctrl-3 = <&i2cmux_s32>; + pinctrl-4 = <&i2cmux_pins_i>; + i2c152: i2c_sfp1 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c153: i2c_sfp2 { + reg = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c154: i2c_sfp3 { + reg = <0x2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c155: i2c_sfp4 { + reg = <0x3>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi index 1f99d0db1284..9d1a082de3e2 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi @@ -13,3 +13,7 @@ &uart0 { &uart1 { status = "okay"; }; + +&i2c0 { + status = "okay"; +}; From f7d85e73f92026e436b0068066cf862c08521818 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 10 Jul 2020 18:45:33 +0900 Subject: [PATCH 14/38] dt-bindings: vendor-prefixes: Add mstar vendor prefix Add prefix for MStar Semiconductor, Inc. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann Acked-by: Rob Herring Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 9aeab66be85f..b09b6c9911c3 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -680,6 +680,8 @@ patternProperties: description: Microsemi Corporation "^msi,.*": description: Micro-Star International Co. Ltd. + "^mstar,.*": + description: MStar Semiconductor, Inc. (acquired by MediaTek Inc.) "^mti,.*": description: Imagination Technologies Ltd. (formerly MIPS Technologies Inc.) "^multi-inno,.*": From 108fc78f16fb070d4e809229e180bcf4effc797e Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 10 Jul 2020 18:45:34 +0900 Subject: [PATCH 15/38] dt-bindings: vendor-prefixes: Add sstar vendor prefix Add prefix for Xiamen Xingchen Technology Co., Ltd Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann Acked-by: Rob Herring Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index b09b6c9911c3..ba5bd3b0ed9a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -986,6 +986,8 @@ patternProperties: description: Spreadtrum Communications Inc. "^sst,.*": description: Silicon Storage Technology, Inc. + "^sstar,.*": + description: Xiamen Xingchen(SigmaStar) Technology Co., Ltd. (formerly part of MStar Semiconductor, Inc.) "^st,.*": description: STMicroelectronics "^starry,.*": From cdef4702e2799a58e32021c345c3a43ca72f9c27 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 10 Jul 2020 18:45:35 +0900 Subject: [PATCH 16/38] dt-bindings: vendor-prefixes: Add 70mai vendor prefix Add prefix for 70mai Co., Ltd Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann Acked-by: Rob Herring Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index ba5bd3b0ed9a..53cd050668e6 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -23,6 +23,8 @@ patternProperties: "^(simple-audio-card|simple-graph-card|st-plgpio|st-spics|ts),.*": true # Keep list in alphabetical order. + "^70mai,.*": + description: 70mai Co., Ltd. "^abilis,.*": description: Abilis Systems "^abracon,.*": From d1b6e3bd85f02e7ead020de9cd87fcd0326ae9ad Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 10 Jul 2020 18:45:36 +0900 Subject: [PATCH 17/38] dt-bindings: vendor-prefixes: Add thingy.jp prefix Add prefix for thingy.jp Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann Acked-by: Rob Herring Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 53cd050668e6..c209b3dc7ecc 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1038,6 +1038,8 @@ patternProperties: description: Three Five Corp "^thine,.*": description: THine Electronics, Inc. + "^thingyjp,.*": + description: thingy.jp "^ti,.*": description: Texas Instruments "^tianma,.*": From 343e8f7286e87f60ef7cc8c8b140e254f550886f Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 10 Jul 2020 18:45:37 +0900 Subject: [PATCH 18/38] dt-bindings: arm: Add mstar YAML schema Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann Reviewed-by: Rob Herring Signed-off-by: Arnd Bergmann --- .../devicetree/bindings/arm/mstar.yaml | 33 +++++++++++++++++++ MAINTAINERS | 7 ++++ 2 files changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mstar.yaml diff --git a/Documentation/devicetree/bindings/arm/mstar.yaml b/Documentation/devicetree/bindings/arm/mstar.yaml new file mode 100644 index 000000000000..bdce34b3336e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mstar.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mstar.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MStar platforms device tree bindings + +maintainers: + - Daniel Palmer + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: infinity boards + items: + - enum: + - thingyjp,breadbee-crust # thingy.jp BreadBee Crust + - const: mstar,infinity + + - description: infinity3 boards + items: + - enum: + - thingyjp,breadbee # thingy.jp BreadBee + - const: mstar,infinity3 + + - description: mercury5 boards + items: + - enum: + - 70mai,midrived08 # 70mai midrive d08 + - const: mstar,mercury5 diff --git a/MAINTAINERS b/MAINTAINERS index fc6b50723c22..d9a4418b4733 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2134,6 +2134,13 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-pxa/mioa701.c +ARM/MStar/Sigmastar Armv7 SoC support +M: Daniel Palmer +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +W: http://linux-chenxing.org/ +F: Documentation/devicetree/bindings/arm/mstar.yaml + ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT M: Michael Petchkovsky S: Maintained From 312b62b6610cabea4cb535fd4889c41e9a84afca Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 10 Jul 2020 18:45:38 +0900 Subject: [PATCH 19/38] ARM: mstar: Add machine for MStar/Sigmastar Armv7 SoCs Initial support for the MStar/Sigmastar Armv7 based IP camera and dashcam SoCs. These chips are interesting in that they contain a Cortex-A7, peripherals and system memory in a single tiny QFN package that can be hand soldered allowing almost anyone to embed Linux in their projects. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- MAINTAINERS | 1 + arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + arch/arm/mach-mstar/Kconfig | 26 ++++++++++++ arch/arm/mach-mstar/Makefile | 1 + arch/arm/mach-mstar/mstarv7.c | 80 +++++++++++++++++++++++++++++++++++ 6 files changed, 111 insertions(+) create mode 100644 arch/arm/mach-mstar/Kconfig create mode 100644 arch/arm/mach-mstar/Makefile create mode 100644 arch/arm/mach-mstar/mstarv7.c diff --git a/MAINTAINERS b/MAINTAINERS index d9a4418b4733..fb7f5310169b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2140,6 +2140,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar.yaml +F: arch/arm/mach-mstar/ ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT M: Michael Petchkovsky diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2ac74904a3ce..d54c413ad937 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -668,6 +668,8 @@ source "arch/arm/mach-mmp/Kconfig" source "arch/arm/mach-moxart/Kconfig" +source "arch/arm/mach-mstar/Kconfig" + source "arch/arm/mach-mv78xx0/Kconfig" source "arch/arm/mach-mvebu/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 59fde2d598d8..e7f4ca060c0f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -197,6 +197,7 @@ machine-$(CONFIG_ARCH_MXC) += imx machine-$(CONFIG_ARCH_MEDIATEK) += mediatek machine-$(CONFIG_ARCH_MILBEAUT) += milbeaut machine-$(CONFIG_ARCH_MXS) += mxs +machine-$(CONFIG_ARCH_MSTARV7) += mstar machine-$(CONFIG_ARCH_NOMADIK) += nomadik machine-$(CONFIG_ARCH_NPCM) += npcm machine-$(CONFIG_ARCH_NSPIRE) += nspire diff --git a/arch/arm/mach-mstar/Kconfig b/arch/arm/mach-mstar/Kconfig new file mode 100644 index 000000000000..52744fe32368 --- /dev/null +++ b/arch/arm/mach-mstar/Kconfig @@ -0,0 +1,26 @@ +menuconfig ARCH_MSTARV7 + bool "MStar/Sigmastar Armv7 SoC Support" + depends on ARCH_MULTI_V7 + select ARM_GIC + select ARM_HEAVY_MB + help + Support for newer MStar/Sigmastar SoC families that are + based on Armv7 cores like the Cortex A7 and share the same + basic hardware like the infinity and mercury series. + +if ARCH_MSTARV7 + +config MACH_INFINITY + bool "MStar/Sigmastar infinity SoC support" + default ARCH_MSTARV7 + help + Support for MStar/Sigmastar infinity IP camera SoCs. + +config MACH_MERCURY + bool "MStar/Sigmastar mercury SoC support" + default ARCH_MSTARV7 + help + Support for MStar/Sigmastar mercury dash camera SoCs. + Note that older Mercury2 SoCs are ARM9 based and not supported. + +endif diff --git a/arch/arm/mach-mstar/Makefile b/arch/arm/mach-mstar/Makefile new file mode 100644 index 000000000000..93b0391ede7e --- /dev/null +++ b/arch/arm/mach-mstar/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_ARCH_MSTARV7) += mstarv7.o diff --git a/arch/arm/mach-mstar/mstarv7.c b/arch/arm/mach-mstar/mstarv7.c new file mode 100644 index 000000000000..81a4cbcab206 --- /dev/null +++ b/arch/arm/mach-mstar/mstarv7.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree support for MStar/Sigmastar Armv7 SoCs + * + * Copyright (c) 2020 thingy.jp + * Author: Daniel Palmer + */ + +#include +#include +#include +#include +#include +#include + +/* + * In the u-boot code the area these registers are in is + * called "L3 bridge" and there are register descriptions + * for something in the same area called "AXI". + * + * It's not exactly known what this is but the vendor code + * for both u-boot and linux share calls to "flush the miu pipe". + * This seems to be to force pending CPU writes to memory so that + * the state is right before DMA capable devices try to read + * descriptors and data the CPU has prepared. Without doing this + * ethernet doesn't work reliably for example. + */ + +#define MSTARV7_L3BRIDGE_FLUSH 0x14 +#define MSTARV7_L3BRIDGE_STATUS 0x40 +#define MSTARV7_L3BRIDGE_FLUSH_TRIGGER BIT(0) +#define MSTARV7_L3BRIDGE_STATUS_DONE BIT(12) + +static void __iomem *l3bridge; + +static const char * const mstarv7_board_dt_compat[] __initconst = { + "mstar,infinity", + "mstar,infinity3", + "mstar,mercury5", + NULL, +}; + +/* + * This may need locking to deal with situations where an interrupt + * happens while we are in here and mb() gets called by the interrupt handler. + * + * The vendor code did have a spin lock but it doesn't seem to be needed and + * removing it hasn't caused any side effects so far. + * + * [writel|readl]_relaxed have to be used here because otherwise + * we'd end up right back in here. + */ +static void mstarv7_mb(void) +{ + /* toggle the flush miu pipe fire bit */ + writel_relaxed(0, l3bridge + MSTARV7_L3BRIDGE_FLUSH); + writel_relaxed(MSTARV7_L3BRIDGE_FLUSH_TRIGGER, l3bridge + + MSTARV7_L3BRIDGE_FLUSH); + while (!(readl_relaxed(l3bridge + MSTARV7_L3BRIDGE_STATUS) + & MSTARV7_L3BRIDGE_STATUS_DONE)) { + /* wait for flush to complete */ + } +} + +static void __init mstarv7_init(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "mstar,l3bridge"); + l3bridge = of_iomap(np, 0); + if (l3bridge) + soc_mb = mstarv7_mb; + else + pr_warn("Failed to install memory barrier, DMA will be broken!\n"); +} + +DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)") + .dt_compat = mstarv7_board_dt_compat, + .init_machine = mstarv7_init, +MACHINE_END From 09220c579c7873a89a07f4f55da9662b1b95355f Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 10 Jul 2020 18:45:39 +0900 Subject: [PATCH 20/38] ARM: mstar: Add binding details for mstar,l3bridge This adds a YAML description of the l3bridge node needed by the platform code for the MStar/SigmaStar Armv7 SoCs. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann Reviewed-by: Rob Herring Signed-off-by: Arnd Bergmann --- .../bindings/misc/mstar,l3bridge.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml diff --git a/Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml b/Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml new file mode 100644 index 000000000000..cb7fd1cdfb1a --- /dev/null +++ b/Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 thingy.jp. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/misc/mstar,l3bridge.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MStar/SigmaStar Armv7 SoC l3bridge + +maintainers: + - Daniel Palmer + +description: | + MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface + between the CPU and memory. This means that before DMA capable + devices are allowed to run the pipeline must be flushed to ensure + everything is in memory. + + The l3bridge region contains registers that allow such a flush + to be triggered. + + This node is used by the platform code to find where the registers + are and install a barrier that triggers the required pipeline flush. + +properties: + compatible: + items: + - const: mstar,l3bridge + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + l3bridge: l3bridge@1f204400 { + compatible = "mstar,l3bridge"; + reg = <0x1f204400 0x200>; + }; From b0d0bb1b6f8700deaf23e8ea42eaca9c54488fc9 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 10 Jul 2020 18:45:40 +0900 Subject: [PATCH 21/38] ARM: mstar: Add Armv7 base dtsi Adds initial dtsi for the base MStar/Sigmastar Armv7 SoCs. These SoCs have very similar memory maps and this will avoid duplicating nodes across multiple dtsis. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- MAINTAINERS | 1 + arch/arm/boot/dts/mstar-v7.dtsi | 83 +++++++++++++++++++++++++++++++++ 2 files changed, 84 insertions(+) create mode 100644 arch/arm/boot/dts/mstar-v7.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index fb7f5310169b..ccabe73ce800 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2140,6 +2140,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar.yaml +F: arch/arm/boot/dts/mstar-v7.dtsi F: arch/arm/mach-mstar/ ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi new file mode 100644 index 000000000000..3b99bb435bb5 --- /dev/null +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + }; + + arch_timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + /* + * we shouldn't need this but the vendor + * u-boot is broken + */ + clock-frequency = <6000000>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x16001000 0x16001000 0x00007000>, + <0x1f000000 0x1f000000 0x00400000>; + + gic: interrupt-controller@16001000 { + compatible = "arm,cortex-a7-gic"; + reg = <0x16001000 0x1000>, + <0x16002000 0x2000>, + <0x16004000 0x2000>, + <0x16006000 0x2000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + riu: bus@1f000000 { + compatible = "simple-bus"; + reg = <0x1f000000 0x00400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1f000000 0x00400000>; + + l3bridge: l3bridge@204400 { + compatible = "mstar,l3bridge"; + reg = <0x204400 0x200>; + }; + + pm_uart: uart@221000 { + compatible = "ns16550a"; + reg = <0x221000 0x100>; + reg-shift = <3>; + clock-frequency = <172000000>; + status = "disabled"; + }; + }; + }; +}; From 952c0ed6f96339ae5d0f22154d05f8eac2742c94 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 10 Jul 2020 18:45:41 +0900 Subject: [PATCH 22/38] ARM: mstar: Add infinity/infinity3 family dtsis This adds two family level dtsis for the infinity and infinity3 and then adds a chip level dtsi each for a chip in those families. infinity3.dtsi includes infinity.dtsi as these SoCs share most of their memory map and we would have a lot of duplication otherwise. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- MAINTAINERS | 1 + arch/arm/boot/dts/infinity-msc313.dtsi | 14 ++++++++++++++ arch/arm/boot/dts/infinity.dtsi | 7 +++++++ arch/arm/boot/dts/infinity3-msc313e.dtsi | 14 ++++++++++++++ arch/arm/boot/dts/infinity3.dtsi | 7 +++++++ 5 files changed, 43 insertions(+) create mode 100644 arch/arm/boot/dts/infinity-msc313.dtsi create mode 100644 arch/arm/boot/dts/infinity.dtsi create mode 100644 arch/arm/boot/dts/infinity3-msc313e.dtsi create mode 100644 arch/arm/boot/dts/infinity3.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index ccabe73ce800..48df02045641 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2140,6 +2140,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar.yaml +F: arch/arm/boot/dts/infinity*.dtsi F: arch/arm/boot/dts/mstar-v7.dtsi F: arch/arm/mach-mstar/ diff --git a/arch/arm/boot/dts/infinity-msc313.dtsi b/arch/arm/boot/dts/infinity-msc313.dtsi new file mode 100644 index 000000000000..42f2b5552c77 --- /dev/null +++ b/arch/arm/boot/dts/infinity-msc313.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "infinity.dtsi" + +/ { + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x4000000>; + }; +}; diff --git a/arch/arm/boot/dts/infinity.dtsi b/arch/arm/boot/dts/infinity.dtsi new file mode 100644 index 000000000000..f68e6d59c328 --- /dev/null +++ b/arch/arm/boot/dts/infinity.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-v7.dtsi" diff --git a/arch/arm/boot/dts/infinity3-msc313e.dtsi b/arch/arm/boot/dts/infinity3-msc313e.dtsi new file mode 100644 index 000000000000..4e7239afd823 --- /dev/null +++ b/arch/arm/boot/dts/infinity3-msc313e.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "infinity3.dtsi" + +/ { + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x4000000>; + }; +}; diff --git a/arch/arm/boot/dts/infinity3.dtsi b/arch/arm/boot/dts/infinity3.dtsi new file mode 100644 index 000000000000..2830d064c07d --- /dev/null +++ b/arch/arm/boot/dts/infinity3.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "infinity.dtsi" From 3e54698c1ae1eaa60d213dc11bede651d9bacb8a Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 10 Jul 2020 18:45:42 +0900 Subject: [PATCH 23/38] ARM: mstar: Add mercury5 series dtsis This adds a family level dtsi for the mercury5 and then a chip level dtsi for the ssc8336n chip. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- MAINTAINERS | 1 + arch/arm/boot/dts/mercury5-ssc8336n.dtsi | 14 ++++++++++++++ arch/arm/boot/dts/mercury5.dtsi | 7 +++++++ 3 files changed, 22 insertions(+) create mode 100644 arch/arm/boot/dts/mercury5-ssc8336n.dtsi create mode 100644 arch/arm/boot/dts/mercury5.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 48df02045641..5cf1f451d62e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2141,6 +2141,7 @@ S: Maintained W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar.yaml F: arch/arm/boot/dts/infinity*.dtsi +F: arch/arm/boot/dts/mercury*.dtsi F: arch/arm/boot/dts/mstar-v7.dtsi F: arch/arm/mach-mstar/ diff --git a/arch/arm/boot/dts/mercury5-ssc8336n.dtsi b/arch/arm/boot/dts/mercury5-ssc8336n.dtsi new file mode 100644 index 000000000000..7d4a4630c25c --- /dev/null +++ b/arch/arm/boot/dts/mercury5-ssc8336n.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mercury5.dtsi" + +/ { + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x4000000>; + }; +}; diff --git a/arch/arm/boot/dts/mercury5.dtsi b/arch/arm/boot/dts/mercury5.dtsi new file mode 100644 index 000000000000..f68e6d59c328 --- /dev/null +++ b/arch/arm/boot/dts/mercury5.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-v7.dtsi" From caa3c193c9dca7b7c672f75c8cb67ee9a7802ffc Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 10 Jul 2020 18:45:43 +0900 Subject: [PATCH 24/38] ARM: mstar: Add dts for msc313(e) based BreadBee boards BreadBee is an opensource development board based on the MStar msc313(e) SoC. Hardware details, schematics and so on can be found at: https://github.com/breadbee/breadbee Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/Makefile | 3 +++ .../dts/infinity-msc313-breadbee_crust.dts | 25 +++++++++++++++++++ .../boot/dts/infinity3-msc313e-breadbee.dts | 25 +++++++++++++++++++ 3 files changed, 53 insertions(+) create mode 100644 arch/arm/boot/dts/infinity-msc313-breadbee_crust.dts create mode 100644 arch/arm/boot/dts/infinity3-msc313e-breadbee.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e6a1cac0bfc7..4a5f8075a4f6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1342,6 +1342,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt8127-moose.dtb \ mt8135-evbp1.dtb dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb +dtb-$(CONFIG_ARCH_MSTARV7) += \ + infinity-msc313-breadbee_crust.dtb \ + infinity3-msc313e-breadbee.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2500-evb.dtb \ diff --git a/arch/arm/boot/dts/infinity-msc313-breadbee_crust.dts b/arch/arm/boot/dts/infinity-msc313-breadbee_crust.dts new file mode 100644 index 000000000000..f24c5580d3e4 --- /dev/null +++ b/arch/arm/boot/dts/infinity-msc313-breadbee_crust.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 thingy.jp. + * Author: Daniel Palmer + */ + +/dts-v1/; +#include "infinity-msc313.dtsi" + +/ { + model = "BreadBee Crust"; + compatible = "thingyjp,breadbee-crust", "mstar,infinity"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/infinity3-msc313e-breadbee.dts b/arch/arm/boot/dts/infinity3-msc313e-breadbee.dts new file mode 100644 index 000000000000..1f93401c8530 --- /dev/null +++ b/arch/arm/boot/dts/infinity3-msc313e-breadbee.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 thingy.jp. + * Author: Daniel Palmer + */ + +/dts-v1/; +#include "infinity3-msc313e.dtsi" + +/ { + model = "BreadBee"; + compatible = "thingyjp,breadbee", "mstar,infinity3"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; From 8484515b96a54ddb3bcaf1f074d52f3af07933d6 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 10 Jul 2020 18:45:44 +0900 Subject: [PATCH 25/38] ARM: mstar: Add dts for 70mai midrive d08 Adds initial support for the 70mai midrive d08 dash camera. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/Makefile | 3 ++- .../boot/dts/mercury5-ssc8336n-midrived08.dts | 25 +++++++++++++++++++ 2 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/mercury5-ssc8336n-midrived08.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4a5f8075a4f6..35c7ecc52c60 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1344,7 +1344,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb dtb-$(CONFIG_ARCH_MSTARV7) += \ infinity-msc313-breadbee_crust.dtb \ - infinity3-msc313e-breadbee.dtb + infinity3-msc313e-breadbee.dtb \ + mercury5-ssc8336n-midrive08.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2500-evb.dtb \ diff --git a/arch/arm/boot/dts/mercury5-ssc8336n-midrived08.dts b/arch/arm/boot/dts/mercury5-ssc8336n-midrived08.dts new file mode 100644 index 000000000000..f24bd8cb8e60 --- /dev/null +++ b/arch/arm/boot/dts/mercury5-ssc8336n-midrived08.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +/dts-v1/; +#include "mercury5-ssc8336n.dtsi" + +/ { + model = "70mai Midrive D08"; + compatible = "70mai,midrived08", "mstar,mercury5"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; From 98895d5e9e195b3f660afd9f04e24d2b307cb660 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Sat, 25 Jul 2020 15:36:39 +0900 Subject: [PATCH 26/38] ARM: mstar: Fix dts filename for 70mai midrive d08 Fixes the filename for the 70mai midrive d08 dts. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 35c7ecc52c60..caf4a47ba799 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1345,7 +1345,7 @@ dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb dtb-$(CONFIG_ARCH_MSTARV7) += \ infinity-msc313-breadbee_crust.dtb \ infinity3-msc313e-breadbee.dtb \ - mercury5-ssc8336n-midrive08.dtb + mercury5-ssc8336n-midrived08.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2500-evb.dtb \ From 33cabc0bc679022160c48f96e2d358e666710f58 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 28 Jul 2020 19:03:13 +0900 Subject: [PATCH 27/38] dt-bindings: arm: mstar: Add binding details for mstar, pmsleep This adds a YAML description of the pmsleep node used by MStar/SigmaStar Armv7 SoCs. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- .../bindings/arm/mstar/mstar,pmsleep.yaml | 43 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mstar/mstar,pmsleep.yaml diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar,pmsleep.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar,pmsleep.yaml new file mode 100644 index 000000000000..ef78097a7087 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mstar/mstar,pmsleep.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 thingy.jp. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mstar/mstar,pmsleep.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MStar/SigmaStar Armv7 SoC pmsleep register region + +maintainers: + - Daniel Palmer + +description: | + MStar/Sigmastar's Armv7 SoCs contain a region of registers that are + in the always on domain that the vendor code calls the "pmsleep" area. + + This area contains registers and bits for a broad range of functionality + ranging from registers that control going into deep sleep to bits that + turn things like the internal temperature sensor on and off. + +properties: + compatible: + oneOf: + - items: + - enum: + - mstar,pmsleep + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pmsleep: pmsleep@1c00 { + compatible = "mstar,pmsleep", "syscon"; + reg = <0x0x1c00 0x100>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 5cf1f451d62e..2de475e12d4f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2140,6 +2140,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar.yaml +F: Documentation/devicetree/bindings/arm/mstar/* F: arch/arm/boot/dts/infinity*.dtsi F: arch/arm/boot/dts/mercury*.dtsi F: arch/arm/boot/dts/mstar-v7.dtsi From 9e30b098f25f525af048e685ccb79fc958cfd200 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 28 Jul 2020 19:03:14 +0900 Subject: [PATCH 28/38] dt-bindings: arm: mstar: Move existing MStar binding descriptions Now there is an mstar directory move the existing MStar specific descriptions into that directory. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- .../devicetree/bindings/{misc => arm/mstar}/mstar,l3bridge.yaml | 2 +- Documentation/devicetree/bindings/arm/{ => mstar}/mstar.yaml | 2 +- MAINTAINERS | 1 - 3 files changed, 2 insertions(+), 3 deletions(-) rename Documentation/devicetree/bindings/{misc => arm/mstar}/mstar,l3bridge.yaml (93%) rename Documentation/devicetree/bindings/arm/{ => mstar}/mstar.yaml (93%) diff --git a/Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar,l3bridge.yaml similarity index 93% rename from Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml rename to Documentation/devicetree/bindings/arm/mstar/mstar,l3bridge.yaml index cb7fd1cdfb1a..6816bd68f9cf 100644 --- a/Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml +++ b/Documentation/devicetree/bindings/arm/mstar/mstar,l3bridge.yaml @@ -2,7 +2,7 @@ # Copyright 2020 thingy.jp. %YAML 1.2 --- -$id: "http://devicetree.org/schemas/misc/mstar,l3bridge.yaml#" +$id: "http://devicetree.org/schemas/arm/mstar/mstar,l3bridge.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: MStar/SigmaStar Armv7 SoC l3bridge diff --git a/Documentation/devicetree/bindings/arm/mstar.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml similarity index 93% rename from Documentation/devicetree/bindings/arm/mstar.yaml rename to Documentation/devicetree/bindings/arm/mstar/mstar.yaml index bdce34b3336e..c2f980b00b06 100644 --- a/Documentation/devicetree/bindings/arm/mstar.yaml +++ b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/mstar.yaml# +$id: http://devicetree.org/schemas/arm/mstar/mstar.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: MStar platforms device tree bindings diff --git a/MAINTAINERS b/MAINTAINERS index 2de475e12d4f..f8e2683d8bff 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2139,7 +2139,6 @@ M: Daniel Palmer L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://linux-chenxing.org/ -F: Documentation/devicetree/bindings/arm/mstar.yaml F: Documentation/devicetree/bindings/arm/mstar/* F: arch/arm/boot/dts/infinity*.dtsi F: arch/arm/boot/dts/mercury*.dtsi From 7f6348b6a5096c46cf5b833d8ea0ae5eeb61e336 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 28 Jul 2020 19:03:15 +0900 Subject: [PATCH 29/38] ARM: mstar: Add IMI SRAM region All MStar v7 SoCs have an internal SRAM region that is between 64KB (infinity2m) and 128KB(infinity3, mercury5). The region is always at the same base address and is used for the second stage loader (MStar IPL or u-boot SPL) and will be used for the DDR self-refresh entry code within the kernel eventually. This patch adds a 128KB region to the SoC and the minimum 64KB SRAM region to the base dtsi. Families with more SRAM will override the size in their family level dtsi. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mstar-v7.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 3b99bb435bb5..1941f88a69a5 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -45,7 +45,8 @@ soc: soc { #address-cells = <1>; #size-cells = <1>; ranges = <0x16001000 0x16001000 0x00007000>, - <0x1f000000 0x1f000000 0x00400000>; + <0x1f000000 0x1f000000 0x00400000>, + <0xa0000000 0xa0000000 0x20000>; gic: interrupt-controller@16001000 { compatible = "arm,cortex-a7-gic"; @@ -79,5 +80,10 @@ pm_uart: uart@221000 { status = "disabled"; }; }; + + imi: sram@a0000000 { + compatible = "mmio-sram"; + reg = <0xa0000000 0x10000>; + }; }; }; From ab6be2008673c6ee5cd7b77946d992bf53ab91db Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 28 Jul 2020 19:03:16 +0900 Subject: [PATCH 30/38] ARM: mstar: Adjust IMI size of infinity infinity has 88KB of SRAM at the IMI region. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/infinity.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/infinity.dtsi b/arch/arm/boot/dts/infinity.dtsi index f68e6d59c328..cd911adef014 100644 --- a/arch/arm/boot/dts/infinity.dtsi +++ b/arch/arm/boot/dts/infinity.dtsi @@ -5,3 +5,7 @@ */ #include "mstar-v7.dtsi" + +&imi { + reg = <0xa0000000 0x16000>; +}; From e709252cac13d9fbba34c6e9d1624f258bf80e89 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 28 Jul 2020 19:03:17 +0900 Subject: [PATCH 31/38] ARM: mstar: Adjust IMI size for mercury5 mercury5 family chips have 128KB of SRAM in the IMI region. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mercury5.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/mercury5.dtsi b/arch/arm/boot/dts/mercury5.dtsi index f68e6d59c328..a7d0dd9d6132 100644 --- a/arch/arm/boot/dts/mercury5.dtsi +++ b/arch/arm/boot/dts/mercury5.dtsi @@ -5,3 +5,7 @@ */ #include "mstar-v7.dtsi" + +&imi { + reg = <0xa0000000 0x20000>; +}; From 6e17d1316d5cdd771f9cd40496d5d740d69ae990 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 28 Jul 2020 19:03:18 +0900 Subject: [PATCH 32/38] ARM: mstar: Adjust IMI size for infinity3 infinity3 has 128KB of SRAM at the IMI region. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/infinity3.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/infinity3.dtsi b/arch/arm/boot/dts/infinity3.dtsi index 2830d064c07d..9b918c802654 100644 --- a/arch/arm/boot/dts/infinity3.dtsi +++ b/arch/arm/boot/dts/infinity3.dtsi @@ -5,3 +5,7 @@ */ #include "infinity.dtsi" + +&imi { + reg = <0xa0000000 0x20000>; +}; From d7f1d81b0fe80a2fdd4485427921b04dbd0ab062 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 28 Jul 2020 19:03:19 +0900 Subject: [PATCH 33/38] ARM: mstar: Add PMU Adds the ARM PMU to the base MStar v7 dtsi. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mstar-v7.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 1941f88a69a5..f787b8e4b67f 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -40,6 +40,12 @@ arch_timer { clock-frequency = <6000000>; }; + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; From 9345a99710aa3a7ad600b2089672cb0f2088f1ff Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 28 Jul 2020 19:03:20 +0900 Subject: [PATCH 34/38] ARM: mstar: Add "pmsleep" node to base dtsi This patch adds a node for the pmsleep area so that other drivers can access registers contained within it. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mstar-v7.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index f787b8e4b67f..bb7fb3e689a7 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -73,6 +73,11 @@ riu: bus@1f000000 { #size-cells = <1>; ranges = <0x0 0x1f000000 0x00400000>; + pmsleep: syscon@1c00 { + compatible = "mstar,pmsleep", "syscon"; + reg = <0x1c00 0x100>; + }; + l3bridge: l3bridge@204400 { compatible = "mstar,l3bridge"; reg = <0x204400 0x200>; From 7e836785bc11aca306ce6acbb43f8a5b5d0a9880 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 28 Jul 2020 19:03:21 +0900 Subject: [PATCH 35/38] ARM: mstar: Add reboot support MStar v7 SoCs support reset by writing a magic value to a register in the "pmsleep" area. This adds a node for using the syscon reboot driver to trigger a reset. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mstar-v7.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index bb7fb3e689a7..c7458c67c4df 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -78,6 +78,13 @@ pmsleep: syscon@1c00 { reg = <0x1c00 0x100>; }; + reboot { + compatible = "syscon-reboot"; + regmap = <&pmsleep>; + offset = <0xb8>; + mask = <0x79>; + }; + l3bridge: l3bridge@204400 { compatible = "mstar,l3bridge"; reg = <0x204400 0x200>; From 4b4b27e4330e8fd0e3b96a2fd801f3ac188f5e79 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Thu, 30 Jul 2020 00:07:46 +0900 Subject: [PATCH 36/38] dt-bindings: mfd: syscon: add compatible string for mstar,msc313-pmsleep Add a compatible string for the pmsleep register region in the MStar MSC313 SoC. Link: https://lore.kernel.org/r/20200729150748.1945589-2-daniel@0x0f.com Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index f3fba860d3cc..614e58bb5d7d 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -39,6 +39,7 @@ properties: - allwinner,sun8i-v3s-system-controller - allwinner,sun50i-a64-system-controller - microchip,sparx5-cpu-syscon + - mstar,msc313-pmsleep - const: syscon From 1eb47d0a80281decf9b5c8cd08a6da932746a908 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Thu, 30 Jul 2020 00:07:47 +0900 Subject: [PATCH 37/38] dt-bindings: arm: mstar: remove the binding description for mstar,pmsleep Remove the unneeded binding description. Compatible string is in mfd/syscon.yaml now. Link: https://lore.kernel.org/r/20200729150748.1945589-3-daniel@0x0f.com Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- .../bindings/arm/mstar/mstar,pmsleep.yaml | 43 ------------------- 1 file changed, 43 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/mstar/mstar,pmsleep.yaml diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar,pmsleep.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar,pmsleep.yaml deleted file mode 100644 index ef78097a7087..000000000000 --- a/Documentation/devicetree/bindings/arm/mstar/mstar,pmsleep.yaml +++ /dev/null @@ -1,43 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -# Copyright 2020 thingy.jp. -%YAML 1.2 ---- -$id: "http://devicetree.org/schemas/arm/mstar/mstar,pmsleep.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" - -title: MStar/SigmaStar Armv7 SoC pmsleep register region - -maintainers: - - Daniel Palmer - -description: | - MStar/Sigmastar's Armv7 SoCs contain a region of registers that are - in the always on domain that the vendor code calls the "pmsleep" area. - - This area contains registers and bits for a broad range of functionality - ranging from registers that control going into deep sleep to bits that - turn things like the internal temperature sensor on and off. - -properties: - compatible: - oneOf: - - items: - - enum: - - mstar,pmsleep - - const: syscon - - reg: - maxItems: 1 - -required: - - compatible - - reg - -additionalProperties: false - -examples: - - | - pmsleep: pmsleep@1c00 { - compatible = "mstar,pmsleep", "syscon"; - reg = <0x0x1c00 0x100>; - }; From 892900a70b6c6664fe9ce0d4e2a5b6b4c821c0e3 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Thu, 30 Jul 2020 00:07:48 +0900 Subject: [PATCH 38/38] ARM: mstar: Correct the compatible string for pmsleep The compatible string for the pmsleep region has changed. Update the MStar/Sigmastar v7 base dtsi with the new string. Link: https://lore.kernel.org/r/20200729150748.1945589-4-daniel@0x0f.com Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mstar-v7.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index c7458c67c4df..3b7b9b793736 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -74,7 +74,7 @@ riu: bus@1f000000 { ranges = <0x0 0x1f000000 0x00400000>; pmsleep: syscon@1c00 { - compatible = "mstar,pmsleep", "syscon"; + compatible = "mstar,msc313-pmsleep", "syscon"; reg = <0x1c00 0x100>; };