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ARM: mvebu: link PCIe controllers to the MSI controller
This commit adjusts the Armada 370 and Armada XP PCIe controllers Device Tree informations to reference their MSI controller. In the case of this platform, the MSI controller is implemented by the MPIC. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Daniel Price <daniel.price@gmail.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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@ -44,6 +44,7 @@ pcie-controller {
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#address-cells = <3>;
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#address-cells = <3>;
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#size-cells = <2>;
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#size-cells = <2>;
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msi-parent = <&mpic>;
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bus-range = <0x00 0xff>;
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bus-range = <0x00 0xff>;
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ranges =
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ranges =
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@ -57,6 +57,7 @@ pcie-controller {
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#address-cells = <3>;
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#address-cells = <3>;
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#size-cells = <2>;
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#size-cells = <2>;
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msi-parent = <&mpic>;
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bus-range = <0x00 0xff>;
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bus-range = <0x00 0xff>;
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ranges =
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ranges =
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@ -58,6 +58,7 @@ pcie-controller {
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#address-cells = <3>;
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#address-cells = <3>;
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#size-cells = <2>;
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#size-cells = <2>;
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msi-parent = <&mpic>;
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bus-range = <0x00 0xff>;
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bus-range = <0x00 0xff>;
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ranges =
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ranges =
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@ -74,6 +74,7 @@ pcie-controller {
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#address-cells = <3>;
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#address-cells = <3>;
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#size-cells = <2>;
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#size-cells = <2>;
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msi-parent = <&mpic>;
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bus-range = <0x00 0xff>;
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bus-range = <0x00 0xff>;
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ranges =
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ranges =
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