mirror of https://gitee.com/openkylin/linux.git
iwlwifi: rename rxq->dma_addr
Rename rxq->dma_addr to rxq->bd_dma to better emphasize that the physical address stands for the receive buffer descriptor's address. Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
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@ -844,7 +844,7 @@ static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
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static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
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{
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iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
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iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);
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iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
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iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
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iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
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@ -486,7 +486,7 @@ int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
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/* Tell device where to find RBD circular buffer in DRAM */
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iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
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(u32)(rxq->dma_addr >> 8));
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(u32)(rxq->bd_dma >> 8));
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/* Tell device where in DRAM to update its Rx status */
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iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
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@ -751,7 +751,7 @@ void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
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}
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dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
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rxq->dma_addr);
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rxq->bd_dma);
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dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
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rxq->rb_stts, rxq->rb_stts_dma);
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rxq->bd = NULL;
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@ -348,7 +348,7 @@ struct iwl_host_cmd {
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/**
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* struct iwl_rx_queue - Rx queue
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* @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
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* @dma_addr: bus address of buffer of receive buffer descriptors (rbd)
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* @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
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* @read: Shared index to newest available Rx buffer
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* @write: Shared index to oldest written Rx packet
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* @free_count: Number of pre-allocated buffers in rx_free
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@ -362,7 +362,7 @@ struct iwl_host_cmd {
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*/
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struct iwl_rx_queue {
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__le32 *bd;
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dma_addr_t dma_addr;
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dma_addr_t bd_dma;
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struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
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struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
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u32 read;
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@ -175,7 +175,7 @@ int iwl_rx_queue_alloc(struct iwl_priv *priv)
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INIT_LIST_HEAD(&rxq->rx_used);
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/* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
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rxq->bd = dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr,
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rxq->bd = dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->bd_dma,
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GFP_KERNEL);
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if (!rxq->bd)
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goto err_bd;
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@ -199,7 +199,7 @@ int iwl_rx_queue_alloc(struct iwl_priv *priv)
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err_rb:
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dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
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rxq->dma_addr);
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rxq->bd_dma);
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err_bd:
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return -ENOMEM;
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}
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@ -1171,7 +1171,7 @@ static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rx
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}
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dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
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rxq->dma_addr);
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rxq->bd_dma);
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dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
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rxq->rb_stts, rxq->rb_stts_dma);
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rxq->bd = NULL;
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