mirror of https://gitee.com/openkylin/linux.git
Merge remote branch 'nouveau/for-airlied' into drm-linus
* nouveau/for-airlied: drm/nouveau: add module option to disable TV detection drm/nouveau: Never evict VRAM buffers to system. drm/nv50: fix connector table parsing for some cards drm/nv50: add a memory barrier to pushbuf submission drm/nouveau: print a message very early during suspend drm/nv04-nv40: Fix up the programmed horizontal sync pulse delay. drm/nouveau: Gigabyte NX85T connector table lies, it has DVI-I not HDMI drm/nouveau: add option to allow override of dcb connector table types drm/nv50: Improve PGRAPH interrupt handling. drm/nv50: Make ctxprog wait until interrupt handler is done. drm/nouveau: Fix fbcon corruption with font width not divisible by 8 drm/nv50: Remove redundant/incorrect ctxvals initialisation.
This commit is contained in:
Dave Airlie
commit
d5e5deddf6
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@ -12,7 +12,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
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nouveau_dp.o nouveau_grctx.o \
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nv04_timer.o \
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nv04_mc.o nv40_mc.o nv50_mc.o \
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nv04_fb.o nv10_fb.o nv40_fb.o \
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nv04_fb.o nv10_fb.o nv40_fb.o nv50_fb.o \
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nv04_fifo.o nv10_fifo.o nv40_fifo.o nv50_fifo.o \
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nv04_graph.o nv10_graph.o nv20_graph.o \
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nv40_graph.o nv50_graph.o \
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@ -5210,6 +5210,21 @@ divine_connector_type(struct nvbios *bios, int index)
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return type;
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}
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static void
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apply_dcb_connector_quirks(struct nvbios *bios, int idx)
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{
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struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx];
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struct drm_device *dev = bios->dev;
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/* Gigabyte NX85T */
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if ((dev->pdev->device == 0x0421) &&
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(dev->pdev->subsystem_vendor == 0x1458) &&
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(dev->pdev->subsystem_device == 0x344c)) {
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if (cte->type == DCB_CONNECTOR_HDMI_1)
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cte->type = DCB_CONNECTOR_DVI_I;
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}
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}
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static void
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parse_dcb_connector_table(struct nvbios *bios)
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{
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@ -5238,13 +5253,14 @@ parse_dcb_connector_table(struct nvbios *bios)
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entry = conntab + conntab[1];
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cte = &ct->entry[0];
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for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) {
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cte->index = i;
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if (conntab[3] == 2)
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cte->entry = ROM16(entry[0]);
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else
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cte->entry = ROM32(entry[0]);
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cte->type = (cte->entry & 0x000000ff) >> 0;
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cte->index = (cte->entry & 0x00000f00) >> 8;
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cte->index2 = (cte->entry & 0x00000f00) >> 8;
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switch (cte->entry & 0x00033000) {
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case 0x00001000:
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cte->gpio_tag = 0x07;
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@ -5266,6 +5282,8 @@ parse_dcb_connector_table(struct nvbios *bios)
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if (cte->type == 0xff)
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continue;
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apply_dcb_connector_quirks(bios, i);
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NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
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i, cte->entry, cte->type, cte->index, cte->gpio_tag);
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@ -5287,10 +5305,16 @@ parse_dcb_connector_table(struct nvbios *bios)
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break;
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default:
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cte->type = divine_connector_type(bios, cte->index);
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NV_WARN(dev, "unknown type, using 0x%02x", cte->type);
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NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type);
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break;
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}
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if (nouveau_override_conntype) {
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int type = divine_connector_type(bios, cte->index);
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if (type != cte->type)
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NV_WARN(dev, " -> type 0x%02x\n", cte->type);
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}
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}
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}
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@ -72,9 +72,10 @@ enum dcb_connector_type {
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};
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struct dcb_connector_table_entry {
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uint8_t index;
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uint32_t entry;
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enum dcb_connector_type type;
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uint8_t index;
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uint8_t index2;
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uint8_t gpio_tag;
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};
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@ -439,8 +439,7 @@ nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
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switch (bo->mem.mem_type) {
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case TTM_PL_VRAM:
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nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT |
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TTM_PL_FLAG_SYSTEM);
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nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT);
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break;
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default:
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nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM);
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@ -302,7 +302,7 @@ nouveau_connector_detect(struct drm_connector *connector)
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detect_analog:
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nv_encoder = find_encoder_by_type(connector, OUTPUT_ANALOG);
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if (!nv_encoder)
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if (!nv_encoder && !nouveau_tv_disable)
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nv_encoder = find_encoder_by_type(connector, OUTPUT_TV);
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if (nv_encoder) {
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struct drm_encoder *encoder = to_drm_encoder(nv_encoder);
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@ -190,6 +190,11 @@ nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo,
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nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8);
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chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max;
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DRM_MEMORYBARRIER();
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/* Flush writes. */
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nouveau_bo_rd32(pb, 0);
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nvchan_wr32(chan, 0x8c, chan->dma.ib_put);
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chan->dma.ib_free--;
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}
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@ -83,6 +83,14 @@ MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
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int nouveau_nofbaccel = 0;
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module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
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MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
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int nouveau_override_conntype = 0;
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module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
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MODULE_PARM_DESC(tv_disable, "Disable TV-out detection\n");
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int nouveau_tv_disable = 0;
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module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
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MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
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"\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
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"\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
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@ -154,9 +162,11 @@ nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
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if (pm_state.event == PM_EVENT_PRETHAW)
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return 0;
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NV_INFO(dev, "Disabling fbcon acceleration...\n");
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fbdev_flags = dev_priv->fbdev_info->flags;
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dev_priv->fbdev_info->flags |= FBINFO_HWACCEL_DISABLED;
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NV_INFO(dev, "Unpinning framebuffer(s)...\n");
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
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struct nouveau_framebuffer *nouveau_fb;
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@ -681,6 +681,7 @@ extern int nouveau_uscript_tmds;
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extern int nouveau_vram_pushbuf;
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extern int nouveau_vram_notify;
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extern int nouveau_fbpercrtc;
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extern int nouveau_tv_disable;
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extern char *nouveau_tv_norm;
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extern int nouveau_reg_debug;
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extern char *nouveau_vbios;
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@ -688,6 +689,7 @@ extern int nouveau_ctxfw;
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extern int nouveau_ignorelid;
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extern int nouveau_nofbaccel;
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extern int nouveau_noaccel;
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extern int nouveau_override_conntype;
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extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
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extern int nouveau_pci_resume(struct pci_dev *pdev);
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@ -926,6 +928,10 @@ extern void nv40_fb_takedown(struct drm_device *);
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extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
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uint32_t, uint32_t);
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/* nv50_fb.c */
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extern int nv50_fb_init(struct drm_device *);
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extern void nv50_fb_takedown(struct drm_device *);
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/* nv04_fifo.c */
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extern int nv04_fifo_init(struct drm_device *);
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extern void nv04_fifo_disable(struct drm_device *);
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@ -311,6 +311,31 @@ nouveau_print_bitfield_names_(uint32_t value,
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#define nouveau_print_bitfield_names(val, namelist) \
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nouveau_print_bitfield_names_((val), (namelist), ARRAY_SIZE(namelist))
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struct nouveau_enum_names {
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uint32_t value;
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const char *name;
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};
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static void
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nouveau_print_enum_names_(uint32_t value,
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const struct nouveau_enum_names *namelist,
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const int namelist_len)
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{
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/*
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* Caller must have already printed the KERN_* log level for us.
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* Also the caller is responsible for adding the newline.
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*/
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int i;
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for (i = 0; i < namelist_len; ++i) {
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if (value == namelist[i].value) {
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printk("%s", namelist[i].name);
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return;
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}
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}
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printk("unknown value 0x%08x", value);
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}
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#define nouveau_print_enum_names(val, namelist) \
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nouveau_print_enum_names_((val), (namelist), ARRAY_SIZE(namelist))
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static int
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nouveau_graph_chid_from_grctx(struct drm_device *dev)
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@ -427,14 +452,16 @@ nouveau_graph_dump_trap_info(struct drm_device *dev, const char *id,
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t nsource = trap->nsource, nstatus = trap->nstatus;
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NV_INFO(dev, "%s - nSource:", id);
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nouveau_print_bitfield_names(nsource, nsource_names);
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printk(", nStatus:");
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if (dev_priv->card_type < NV_10)
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nouveau_print_bitfield_names(nstatus, nstatus_names);
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else
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nouveau_print_bitfield_names(nstatus, nstatus_names_nv10);
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printk("\n");
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if (dev_priv->card_type < NV_50) {
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NV_INFO(dev, "%s - nSource:", id);
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nouveau_print_bitfield_names(nsource, nsource_names);
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printk(", nStatus:");
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if (dev_priv->card_type < NV_10)
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nouveau_print_bitfield_names(nstatus, nstatus_names);
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else
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nouveau_print_bitfield_names(nstatus, nstatus_names_nv10);
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printk("\n");
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}
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NV_INFO(dev, "%s - Ch %d/%d Class 0x%04x Mthd 0x%04x "
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"Data 0x%08x:0x%08x\n",
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@ -577,28 +604,503 @@ nouveau_pgraph_irq_handler(struct drm_device *dev)
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nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
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}
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static void
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nv50_pfb_vm_trap(struct drm_device *dev, int display, const char *name)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t trap[6];
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int i, ch;
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uint32_t idx = nv_rd32(dev, 0x100c90);
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if (idx & 0x80000000) {
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idx &= 0xffffff;
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if (display) {
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for (i = 0; i < 6; i++) {
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nv_wr32(dev, 0x100c90, idx | i << 24);
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trap[i] = nv_rd32(dev, 0x100c94);
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||||
}
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||||
for (ch = 0; ch < dev_priv->engine.fifo.channels; ch++) {
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||||
struct nouveau_channel *chan = dev_priv->fifos[ch];
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||||
|
||||
if (!chan || !chan->ramin)
|
||||
continue;
|
||||
|
||||
if (trap[1] == chan->ramin->instance >> 12)
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||||
break;
|
||||
}
|
||||
NV_INFO(dev, "%s - VM: Trapped %s at %02x%04x%04x status %08x %08x channel %d\n",
|
||||
name, (trap[5]&0x100?"read":"write"),
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||||
trap[5]&0xff, trap[4]&0xffff,
|
||||
trap[3]&0xffff, trap[0], trap[2], ch);
|
||||
}
|
||||
nv_wr32(dev, 0x100c90, idx | 0x80000000);
|
||||
} else if (display) {
|
||||
NV_INFO(dev, "%s - no VM fault?\n", name);
|
||||
}
|
||||
}
|
||||
|
||||
static struct nouveau_enum_names nv50_mp_exec_error_names[] =
|
||||
{
|
||||
{ 3, "STACK_UNDERFLOW" },
|
||||
{ 4, "QUADON_ACTIVE" },
|
||||
{ 8, "TIMEOUT" },
|
||||
{ 0x10, "INVALID_OPCODE" },
|
||||
{ 0x40, "BREAKPOINT" },
|
||||
};
|
||||
|
||||
static void
|
||||
nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
uint32_t units = nv_rd32(dev, 0x1540);
|
||||
uint32_t addr, mp10, status, pc, oplow, ophigh;
|
||||
int i;
|
||||
int mps = 0;
|
||||
for (i = 0; i < 4; i++) {
|
||||
if (!(units & 1 << (i+24)))
|
||||
continue;
|
||||
if (dev_priv->chipset < 0xa0)
|
||||
addr = 0x408200 + (tpid << 12) + (i << 7);
|
||||
else
|
||||
addr = 0x408100 + (tpid << 11) + (i << 7);
|
||||
mp10 = nv_rd32(dev, addr + 0x10);
|
||||
status = nv_rd32(dev, addr + 0x14);
|
||||
if (!status)
|
||||
continue;
|
||||
if (display) {
|
||||
nv_rd32(dev, addr + 0x20);
|
||||
pc = nv_rd32(dev, addr + 0x24);
|
||||
oplow = nv_rd32(dev, addr + 0x70);
|
||||
ophigh= nv_rd32(dev, addr + 0x74);
|
||||
NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
|
||||
"TP %d MP %d: ", tpid, i);
|
||||
nouveau_print_enum_names(status,
|
||||
nv50_mp_exec_error_names);
|
||||
printk(" at %06x warp %d, opcode %08x %08x\n",
|
||||
pc&0xffffff, pc >> 24,
|
||||
oplow, ophigh);
|
||||
}
|
||||
nv_wr32(dev, addr + 0x10, mp10);
|
||||
nv_wr32(dev, addr + 0x14, 0);
|
||||
mps++;
|
||||
}
|
||||
if (!mps && display)
|
||||
NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
|
||||
"No MPs claiming errors?\n", tpid);
|
||||
}
|
||||
|
||||
static void
|
||||
nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
|
||||
uint32_t ustatus_new, int display, const char *name)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
int tps = 0;
|
||||
uint32_t units = nv_rd32(dev, 0x1540);
|
||||
int i, r;
|
||||
uint32_t ustatus_addr, ustatus;
|
||||
for (i = 0; i < 16; i++) {
|
||||
if (!(units & (1 << i)))
|
||||
continue;
|
||||
if (dev_priv->chipset < 0xa0)
|
||||
ustatus_addr = ustatus_old + (i << 12);
|
||||
else
|
||||
ustatus_addr = ustatus_new + (i << 11);
|
||||
ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
|
||||
if (!ustatus)
|
||||
continue;
|
||||
tps++;
|
||||
switch (type) {
|
||||
case 6: /* texture error... unknown for now */
|
||||
nv50_pfb_vm_trap(dev, display, name);
|
||||
if (display) {
|
||||
NV_ERROR(dev, "magic set %d:\n", i);
|
||||
for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
|
||||
NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
|
||||
nv_rd32(dev, r));
|
||||
}
|
||||
break;
|
||||
case 7: /* MP error */
|
||||
if (ustatus & 0x00010000) {
|
||||
nv50_pgraph_mp_trap(dev, i, display);
|
||||
ustatus &= ~0x00010000;
|
||||
}
|
||||
break;
|
||||
case 8: /* TPDMA error */
|
||||
{
|
||||
uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
|
||||
uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
|
||||
uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
|
||||
uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
|
||||
uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
|
||||
uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
|
||||
uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
|
||||
nv50_pfb_vm_trap(dev, display, name);
|
||||
/* 2d engine destination */
|
||||
if (ustatus & 0x00000010) {
|
||||
if (display) {
|
||||
NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
|
||||
i, e14, e10);
|
||||
NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
|
||||
i, e0c, e18, e1c, e20, e24);
|
||||
}
|
||||
ustatus &= ~0x00000010;
|
||||
}
|
||||
/* Render target */
|
||||
if (ustatus & 0x00000040) {
|
||||
if (display) {
|
||||
NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
|
||||
i, e14, e10);
|
||||
NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
|
||||
i, e0c, e18, e1c, e20, e24);
|
||||
}
|
||||
ustatus &= ~0x00000040;
|
||||
}
|
||||
/* CUDA memory: l[], g[] or stack. */
|
||||
if (ustatus & 0x00000080) {
|
||||
if (display) {
|
||||
if (e18 & 0x80000000) {
|
||||
/* g[] read fault? */
|
||||
NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
|
||||
i, e14, e10 | ((e18 >> 24) & 0x1f));
|
||||
e18 &= ~0x1f000000;
|
||||
} else if (e18 & 0xc) {
|
||||
/* g[] write fault? */
|
||||
NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
|
||||
i, e14, e10 | ((e18 >> 7) & 0x1f));
|
||||
e18 &= ~0x00000f80;
|
||||
} else {
|
||||
NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
|
||||
i, e14, e10);
|
||||
}
|
||||
NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
|
||||
i, e0c, e18, e1c, e20, e24);
|
||||
}
|
||||
ustatus &= ~0x00000080;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
if (ustatus) {
|
||||
if (display)
|
||||
NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
|
||||
}
|
||||
nv_wr32(dev, ustatus_addr, 0xc0000000);
|
||||
}
|
||||
|
||||
if (!tps && display)
|
||||
NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
|
||||
}
|
||||
|
||||
static void
|
||||
nv50_pgraph_trap_handler(struct drm_device *dev)
|
||||
{
|
||||
struct nouveau_pgraph_trap trap;
|
||||
uint32_t status = nv_rd32(dev, 0x400108);
|
||||
uint32_t ustatus;
|
||||
int display = nouveau_ratelimit();
|
||||
|
||||
|
||||
if (!status && display) {
|
||||
nouveau_graph_trap_info(dev, &trap);
|
||||
nouveau_graph_dump_trap_info(dev, "PGRAPH_TRAP", &trap);
|
||||
NV_INFO(dev, "PGRAPH_TRAP - no units reporting traps?\n");
|
||||
}
|
||||
|
||||
/* DISPATCH: Relays commands to other units and handles NOTIFY,
|
||||
* COND, QUERY. If you get a trap from it, the command is still stuck
|
||||
* in DISPATCH and you need to do something about it. */
|
||||
if (status & 0x001) {
|
||||
ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
|
||||
if (!ustatus && display) {
|
||||
NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
|
||||
}
|
||||
|
||||
/* Known to be triggered by screwed up NOTIFY and COND... */
|
||||
if (ustatus & 0x00000001) {
|
||||
nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_DISPATCH_FAULT");
|
||||
nv_wr32(dev, 0x400500, 0);
|
||||
if (nv_rd32(dev, 0x400808) & 0x80000000) {
|
||||
if (display) {
|
||||
if (nouveau_graph_trapped_channel(dev, &trap.channel))
|
||||
trap.channel = -1;
|
||||
trap.class = nv_rd32(dev, 0x400814);
|
||||
trap.mthd = nv_rd32(dev, 0x400808) & 0x1ffc;
|
||||
trap.subc = (nv_rd32(dev, 0x400808) >> 16) & 0x7;
|
||||
trap.data = nv_rd32(dev, 0x40080c);
|
||||
trap.data2 = nv_rd32(dev, 0x400810);
|
||||
nouveau_graph_dump_trap_info(dev,
|
||||
"PGRAPH_TRAP_DISPATCH_FAULT", &trap);
|
||||
NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - 400808: %08x\n", nv_rd32(dev, 0x400808));
|
||||
NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - 400848: %08x\n", nv_rd32(dev, 0x400848));
|
||||
}
|
||||
nv_wr32(dev, 0x400808, 0);
|
||||
} else if (display) {
|
||||
NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - No stuck command?\n");
|
||||
}
|
||||
nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
|
||||
nv_wr32(dev, 0x400848, 0);
|
||||
ustatus &= ~0x00000001;
|
||||
}
|
||||
if (ustatus & 0x00000002) {
|
||||
nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_DISPATCH_QUERY");
|
||||
nv_wr32(dev, 0x400500, 0);
|
||||
if (nv_rd32(dev, 0x40084c) & 0x80000000) {
|
||||
if (display) {
|
||||
if (nouveau_graph_trapped_channel(dev, &trap.channel))
|
||||
trap.channel = -1;
|
||||
trap.class = nv_rd32(dev, 0x400814);
|
||||
trap.mthd = nv_rd32(dev, 0x40084c) & 0x1ffc;
|
||||
trap.subc = (nv_rd32(dev, 0x40084c) >> 16) & 0x7;
|
||||
trap.data = nv_rd32(dev, 0x40085c);
|
||||
trap.data2 = 0;
|
||||
nouveau_graph_dump_trap_info(dev,
|
||||
"PGRAPH_TRAP_DISPATCH_QUERY", &trap);
|
||||
NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_QUERY - 40084c: %08x\n", nv_rd32(dev, 0x40084c));
|
||||
}
|
||||
nv_wr32(dev, 0x40084c, 0);
|
||||
} else if (display) {
|
||||
NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_QUERY - No stuck command?\n");
|
||||
}
|
||||
ustatus &= ~0x00000002;
|
||||
}
|
||||
if (ustatus && display)
|
||||
NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - Unhandled ustatus 0x%08x\n", ustatus);
|
||||
nv_wr32(dev, 0x400804, 0xc0000000);
|
||||
nv_wr32(dev, 0x400108, 0x001);
|
||||
status &= ~0x001;
|
||||
}
|
||||
|
||||
/* TRAPs other than dispatch use the "normal" trap regs. */
|
||||
if (status && display) {
|
||||
nouveau_graph_trap_info(dev, &trap);
|
||||
nouveau_graph_dump_trap_info(dev,
|
||||
"PGRAPH_TRAP", &trap);
|
||||
}
|
||||
|
||||
/* M2MF: Memory to memory copy engine. */
|
||||
if (status & 0x002) {
|
||||
ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
|
||||
if (!ustatus && display) {
|
||||
NV_INFO(dev, "PGRAPH_TRAP_M2MF - no ustatus?\n");
|
||||
}
|
||||
if (ustatus & 0x00000001) {
|
||||
nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_NOTIFY");
|
||||
ustatus &= ~0x00000001;
|
||||
}
|
||||
if (ustatus & 0x00000002) {
|
||||
nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_IN");
|
||||
ustatus &= ~0x00000002;
|
||||
}
|
||||
if (ustatus & 0x00000004) {
|
||||
nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_OUT");
|
||||
ustatus &= ~0x00000004;
|
||||
}
|
||||
NV_INFO (dev, "PGRAPH_TRAP_M2MF - %08x %08x %08x %08x\n",
|
||||
nv_rd32(dev, 0x406804),
|
||||
nv_rd32(dev, 0x406808),
|
||||
nv_rd32(dev, 0x40680c),
|
||||
nv_rd32(dev, 0x406810));
|
||||
if (ustatus && display)
|
||||
NV_INFO(dev, "PGRAPH_TRAP_M2MF - Unhandled ustatus 0x%08x\n", ustatus);
|
||||
/* No sane way found yet -- just reset the bugger. */
|
||||
nv_wr32(dev, 0x400040, 2);
|
||||
nv_wr32(dev, 0x400040, 0);
|
||||
nv_wr32(dev, 0x406800, 0xc0000000);
|
||||
nv_wr32(dev, 0x400108, 0x002);
|
||||
status &= ~0x002;
|
||||
}
|
||||
|
||||
/* VFETCH: Fetches data from vertex buffers. */
|
||||
if (status & 0x004) {
|
||||
ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
|
||||
if (!ustatus && display) {
|
||||
NV_INFO(dev, "PGRAPH_TRAP_VFETCH - no ustatus?\n");
|
||||
}
|
||||
if (ustatus & 0x00000001) {
|
||||
nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_VFETCH_FAULT");
|
||||
NV_INFO (dev, "PGRAPH_TRAP_VFETCH_FAULT - %08x %08x %08x %08x\n",
|
||||
nv_rd32(dev, 0x400c00),
|
||||
nv_rd32(dev, 0x400c08),
|
||||
nv_rd32(dev, 0x400c0c),
|
||||
nv_rd32(dev, 0x400c10));
|
||||
ustatus &= ~0x00000001;
|
||||
}
|
||||
if (ustatus && display)
|
||||
NV_INFO(dev, "PGRAPH_TRAP_VFETCH - Unhandled ustatus 0x%08x\n", ustatus);
|
||||
nv_wr32(dev, 0x400c04, 0xc0000000);
|
||||
nv_wr32(dev, 0x400108, 0x004);
|
||||
status &= ~0x004;
|
||||
}
|
||||
|
||||
/* STRMOUT: DirectX streamout / OpenGL transform feedback. */
|
||||
if (status & 0x008) {
|
||||
ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
|
||||
if (!ustatus && display) {
|
||||
NV_INFO(dev, "PGRAPH_TRAP_STRMOUT - no ustatus?\n");
|
||||
}
|
||||
if (ustatus & 0x00000001) {
|
||||
nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_STRMOUT_FAULT");
|
||||
NV_INFO (dev, "PGRAPH_TRAP_STRMOUT_FAULT - %08x %08x %08x %08x\n",
|
||||
nv_rd32(dev, 0x401804),
|
||||
nv_rd32(dev, 0x401808),
|
||||
nv_rd32(dev, 0x40180c),
|
||||
nv_rd32(dev, 0x401810));
|
||||
ustatus &= ~0x00000001;
|
||||
}
|
||||
if (ustatus && display)
|
||||
NV_INFO(dev, "PGRAPH_TRAP_STRMOUT - Unhandled ustatus 0x%08x\n", ustatus);
|
||||
/* No sane way found yet -- just reset the bugger. */
|
||||
nv_wr32(dev, 0x400040, 0x80);
|
||||
nv_wr32(dev, 0x400040, 0);
|
||||
nv_wr32(dev, 0x401800, 0xc0000000);
|
||||
nv_wr32(dev, 0x400108, 0x008);
|
||||
status &= ~0x008;
|
||||
}
|
||||
|
||||
/* CCACHE: Handles code and c[] caches and fills them. */
|
||||
if (status & 0x010) {
|
||||
ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
|
||||
if (!ustatus && display) {
|
||||
NV_INFO(dev, "PGRAPH_TRAP_CCACHE - no ustatus?\n");
|
||||
}
|
||||
if (ustatus & 0x00000001) {
|
||||
nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_CCACHE_FAULT");
|
||||
NV_INFO (dev, "PGRAPH_TRAP_CCACHE_FAULT - %08x %08x %08x %08x %08x %08x %08x\n",
|
||||
nv_rd32(dev, 0x405800),
|
||||
nv_rd32(dev, 0x405804),
|
||||
nv_rd32(dev, 0x405808),
|
||||
nv_rd32(dev, 0x40580c),
|
||||
nv_rd32(dev, 0x405810),
|
||||
nv_rd32(dev, 0x405814),
|
||||
nv_rd32(dev, 0x40581c));
|
||||
ustatus &= ~0x00000001;
|
||||
}
|
||||
if (ustatus && display)
|
||||
NV_INFO(dev, "PGRAPH_TRAP_CCACHE - Unhandled ustatus 0x%08x\n", ustatus);
|
||||
nv_wr32(dev, 0x405018, 0xc0000000);
|
||||
nv_wr32(dev, 0x400108, 0x010);
|
||||
status &= ~0x010;
|
||||
}
|
||||
|
||||
/* Unknown, not seen yet... 0x402000 is the only trap status reg
|
||||
* remaining, so try to handle it anyway. Perhaps related to that
|
||||
* unknown DMA slot on tesla? */
|
||||
if (status & 0x20) {
|
||||
nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_UNKC04");
|
||||
ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
|
||||
if (display)
|
||||
NV_INFO(dev, "PGRAPH_TRAP_UNKC04 - Unhandled ustatus 0x%08x\n", ustatus);
|
||||
nv_wr32(dev, 0x402000, 0xc0000000);
|
||||
/* no status modifiction on purpose */
|
||||
}
|
||||
|
||||
/* TEXTURE: CUDA texturing units */
|
||||
if (status & 0x040) {
|
||||
nv50_pgraph_tp_trap (dev, 6, 0x408900, 0x408600, display,
|
||||
"PGRAPH_TRAP_TEXTURE");
|
||||
nv_wr32(dev, 0x400108, 0x040);
|
||||
status &= ~0x040;
|
||||
}
|
||||
|
||||
/* MP: CUDA execution engines. */
|
||||
if (status & 0x080) {
|
||||
nv50_pgraph_tp_trap (dev, 7, 0x408314, 0x40831c, display,
|
||||
"PGRAPH_TRAP_MP");
|
||||
nv_wr32(dev, 0x400108, 0x080);
|
||||
status &= ~0x080;
|
||||
}
|
||||
|
||||
/* TPDMA: Handles TP-initiated uncached memory accesses:
|
||||
* l[], g[], stack, 2d surfaces, render targets. */
|
||||
if (status & 0x100) {
|
||||
nv50_pgraph_tp_trap (dev, 8, 0x408e08, 0x408708, display,
|
||||
"PGRAPH_TRAP_TPDMA");
|
||||
nv_wr32(dev, 0x400108, 0x100);
|
||||
status &= ~0x100;
|
||||
}
|
||||
|
||||
if (status) {
|
||||
if (display)
|
||||
NV_INFO(dev, "PGRAPH_TRAP - Unknown trap 0x%08x\n",
|
||||
status);
|
||||
nv_wr32(dev, 0x400108, status);
|
||||
}
|
||||
}
|
||||
|
||||
/* There must be a *lot* of these. Will take some time to gather them up. */
|
||||
static struct nouveau_enum_names nv50_data_error_names[] =
|
||||
{
|
||||
{ 4, "INVALID_VALUE" },
|
||||
{ 5, "INVALID_ENUM" },
|
||||
{ 8, "INVALID_OBJECT" },
|
||||
{ 0xc, "INVALID_BITFIELD" },
|
||||
{ 0x28, "MP_NO_REG_SPACE" },
|
||||
{ 0x2b, "MP_BLOCK_SIZE_MISMATCH" },
|
||||
};
|
||||
|
||||
static void
|
||||
nv50_pgraph_irq_handler(struct drm_device *dev)
|
||||
{
|
||||
struct nouveau_pgraph_trap trap;
|
||||
int unhandled = 0;
|
||||
uint32_t status;
|
||||
|
||||
while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) {
|
||||
uint32_t nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
|
||||
|
||||
/* NOTIFY: You've set a NOTIFY an a command and it's done. */
|
||||
if (status & 0x00000001) {
|
||||
nouveau_pgraph_intr_notify(dev, nsource);
|
||||
nouveau_graph_trap_info(dev, &trap);
|
||||
if (nouveau_ratelimit())
|
||||
nouveau_graph_dump_trap_info(dev,
|
||||
"PGRAPH_NOTIFY", &trap);
|
||||
status &= ~0x00000001;
|
||||
nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000001);
|
||||
}
|
||||
|
||||
if (status & 0x00000010) {
|
||||
nouveau_pgraph_intr_error(dev, nsource |
|
||||
NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD);
|
||||
/* COMPUTE_QUERY: Purpose and exact cause unknown, happens
|
||||
* when you write 0x200 to 0x50c0 method 0x31c. */
|
||||
if (status & 0x00000002) {
|
||||
nouveau_graph_trap_info(dev, &trap);
|
||||
if (nouveau_ratelimit())
|
||||
nouveau_graph_dump_trap_info(dev,
|
||||
"PGRAPH_COMPUTE_QUERY", &trap);
|
||||
status &= ~0x00000002;
|
||||
nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000002);
|
||||
}
|
||||
|
||||
/* Unknown, never seen: 0x4 */
|
||||
|
||||
/* ILLEGAL_MTHD: You used a wrong method for this class. */
|
||||
if (status & 0x00000010) {
|
||||
nouveau_graph_trap_info(dev, &trap);
|
||||
if (nouveau_pgraph_intr_swmthd(dev, &trap))
|
||||
unhandled = 1;
|
||||
if (unhandled && nouveau_ratelimit())
|
||||
nouveau_graph_dump_trap_info(dev,
|
||||
"PGRAPH_ILLEGAL_MTHD", &trap);
|
||||
status &= ~0x00000010;
|
||||
nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000010);
|
||||
}
|
||||
|
||||
/* ILLEGAL_CLASS: You used a wrong class. */
|
||||
if (status & 0x00000020) {
|
||||
nouveau_graph_trap_info(dev, &trap);
|
||||
if (nouveau_ratelimit())
|
||||
nouveau_graph_dump_trap_info(dev,
|
||||
"PGRAPH_ILLEGAL_CLASS", &trap);
|
||||
status &= ~0x00000020;
|
||||
nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000020);
|
||||
}
|
||||
|
||||
/* DOUBLE_NOTIFY: You tried to set a NOTIFY on another NOTIFY. */
|
||||
if (status & 0x00000040) {
|
||||
nouveau_graph_trap_info(dev, &trap);
|
||||
if (nouveau_ratelimit())
|
||||
nouveau_graph_dump_trap_info(dev,
|
||||
"PGRAPH_DOUBLE_NOTIFY", &trap);
|
||||
status &= ~0x00000040;
|
||||
nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000040);
|
||||
}
|
||||
|
||||
/* CONTEXT_SWITCH: PGRAPH needs us to load a new context */
|
||||
if (status & 0x00001000) {
|
||||
nv_wr32(dev, 0x400500, 0x00000000);
|
||||
nv_wr32(dev, NV03_PGRAPH_INTR,
|
||||
|
|
@ -613,49 +1115,59 @@ nv50_pgraph_irq_handler(struct drm_device *dev)
|
|||
status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
|
||||
}
|
||||
|
||||
if (status & 0x00100000) {
|
||||
nouveau_pgraph_intr_error(dev, nsource |
|
||||
NV03_PGRAPH_NSOURCE_DATA_ERROR);
|
||||
/* BUFFER_NOTIFY: Your m2mf transfer finished */
|
||||
if (status & 0x00010000) {
|
||||
nouveau_graph_trap_info(dev, &trap);
|
||||
if (nouveau_ratelimit())
|
||||
nouveau_graph_dump_trap_info(dev,
|
||||
"PGRAPH_BUFFER_NOTIFY", &trap);
|
||||
status &= ~0x00010000;
|
||||
nv_wr32(dev, NV03_PGRAPH_INTR, 0x00010000);
|
||||
}
|
||||
|
||||
/* DATA_ERROR: Invalid value for this method, or invalid
|
||||
* state in current PGRAPH context for this operation */
|
||||
if (status & 0x00100000) {
|
||||
nouveau_graph_trap_info(dev, &trap);
|
||||
if (nouveau_ratelimit()) {
|
||||
nouveau_graph_dump_trap_info(dev,
|
||||
"PGRAPH_DATA_ERROR", &trap);
|
||||
NV_INFO (dev, "PGRAPH_DATA_ERROR - ");
|
||||
nouveau_print_enum_names(nv_rd32(dev, 0x400110),
|
||||
nv50_data_error_names);
|
||||
printk("\n");
|
||||
}
|
||||
status &= ~0x00100000;
|
||||
nv_wr32(dev, NV03_PGRAPH_INTR, 0x00100000);
|
||||
}
|
||||
|
||||
/* TRAP: Something bad happened in the middle of command
|
||||
* execution. Has a billion types, subtypes, and even
|
||||
* subsubtypes. */
|
||||
if (status & 0x00200000) {
|
||||
int r;
|
||||
|
||||
nouveau_pgraph_intr_error(dev, nsource |
|
||||
NV03_PGRAPH_NSOURCE_PROTECTION_ERROR);
|
||||
|
||||
NV_ERROR(dev, "magic set 1:\n");
|
||||
for (r = 0x408900; r <= 0x408910; r += 4)
|
||||
NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
|
||||
nv_rd32(dev, r));
|
||||
nv_wr32(dev, 0x408900,
|
||||
nv_rd32(dev, 0x408904) | 0xc0000000);
|
||||
for (r = 0x408e08; r <= 0x408e24; r += 4)
|
||||
NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
|
||||
nv_rd32(dev, r));
|
||||
nv_wr32(dev, 0x408e08,
|
||||
nv_rd32(dev, 0x408e08) | 0xc0000000);
|
||||
|
||||
NV_ERROR(dev, "magic set 2:\n");
|
||||
for (r = 0x409900; r <= 0x409910; r += 4)
|
||||
NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
|
||||
nv_rd32(dev, r));
|
||||
nv_wr32(dev, 0x409900,
|
||||
nv_rd32(dev, 0x409904) | 0xc0000000);
|
||||
for (r = 0x409e08; r <= 0x409e24; r += 4)
|
||||
NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
|
||||
nv_rd32(dev, r));
|
||||
nv_wr32(dev, 0x409e08,
|
||||
nv_rd32(dev, 0x409e08) | 0xc0000000);
|
||||
|
||||
nv50_pgraph_trap_handler(dev);
|
||||
status &= ~0x00200000;
|
||||
nv_wr32(dev, NV03_PGRAPH_NSOURCE, nsource);
|
||||
nv_wr32(dev, NV03_PGRAPH_INTR, 0x00200000);
|
||||
}
|
||||
|
||||
/* Unknown, never seen: 0x00400000 */
|
||||
|
||||
/* SINGLE_STEP: Happens on every method if you turned on
|
||||
* single stepping in 40008c */
|
||||
if (status & 0x01000000) {
|
||||
nouveau_graph_trap_info(dev, &trap);
|
||||
if (nouveau_ratelimit())
|
||||
nouveau_graph_dump_trap_info(dev,
|
||||
"PGRAPH_SINGLE_STEP", &trap);
|
||||
status &= ~0x01000000;
|
||||
nv_wr32(dev, NV03_PGRAPH_INTR, 0x01000000);
|
||||
}
|
||||
|
||||
/* 0x02000000 happens when you pause a ctxprog...
|
||||
* but the only way this can happen that I know is by
|
||||
* poking the relevant MMIO register, and we don't
|
||||
* do that. */
|
||||
|
||||
if (status) {
|
||||
NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n",
|
||||
status);
|
||||
|
|
@ -672,7 +1184,8 @@ nv50_pgraph_irq_handler(struct drm_device *dev)
|
|||
}
|
||||
|
||||
nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
|
||||
nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
|
||||
if (nv_rd32(dev, 0x400824) & (1 << 31))
|
||||
nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
|
|||
|
|
@ -35,7 +35,6 @@
|
|||
#include "nouveau_drm.h"
|
||||
#include "nv50_display.h"
|
||||
|
||||
static int nouveau_stub_init(struct drm_device *dev) { return 0; }
|
||||
static void nouveau_stub_takedown(struct drm_device *dev) {}
|
||||
|
||||
static int nouveau_init_engine_ptrs(struct drm_device *dev)
|
||||
|
|
@ -277,8 +276,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
|
|||
engine->timer.init = nv04_timer_init;
|
||||
engine->timer.read = nv04_timer_read;
|
||||
engine->timer.takedown = nv04_timer_takedown;
|
||||
engine->fb.init = nouveau_stub_init;
|
||||
engine->fb.takedown = nouveau_stub_takedown;
|
||||
engine->fb.init = nv50_fb_init;
|
||||
engine->fb.takedown = nv50_fb_takedown;
|
||||
engine->graph.grclass = nv50_graph_grclass;
|
||||
engine->graph.init = nv50_graph_init;
|
||||
engine->graph.takedown = nv50_graph_takedown;
|
||||
|
|
|
|||
|
|
@ -230,9 +230,9 @@ nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
|
|||
struct drm_framebuffer *fb = crtc->fb;
|
||||
|
||||
/* Calculate our timings */
|
||||
int horizDisplay = (mode->crtc_hdisplay >> 3) - 1;
|
||||
int horizStart = (mode->crtc_hsync_start >> 3) - 1;
|
||||
int horizEnd = (mode->crtc_hsync_end >> 3) - 1;
|
||||
int horizDisplay = (mode->crtc_hdisplay >> 3) - 1;
|
||||
int horizStart = (mode->crtc_hsync_start >> 3) + 1;
|
||||
int horizEnd = (mode->crtc_hsync_end >> 3) + 1;
|
||||
int horizTotal = (mode->crtc_htotal >> 3) - 5;
|
||||
int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1;
|
||||
int horizBlankEnd = (mode->crtc_htotal >> 3) - 1;
|
||||
|
|
|
|||
|
|
@ -118,8 +118,8 @@ nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
|
|||
return;
|
||||
}
|
||||
|
||||
width = ALIGN(image->width, 32);
|
||||
dsize = (width * image->height) >> 5;
|
||||
width = ALIGN(image->width, 8);
|
||||
dsize = ALIGN(width * image->height, 32) >> 5;
|
||||
|
||||
if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
|
||||
info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
|
||||
|
|
@ -136,8 +136,8 @@ nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
|
|||
((image->dx + image->width) & 0xffff));
|
||||
OUT_RING(chan, bg);
|
||||
OUT_RING(chan, fg);
|
||||
OUT_RING(chan, (image->height << 16) | image->width);
|
||||
OUT_RING(chan, (image->height << 16) | width);
|
||||
OUT_RING(chan, (image->height << 16) | image->width);
|
||||
OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));
|
||||
|
||||
while (dsize) {
|
||||
|
|
|
|||
|
|
@ -522,8 +522,8 @@ int nv50_display_create(struct drm_device *dev)
|
|||
}
|
||||
|
||||
for (i = 0 ; i < dcb->connector.entries; i++) {
|
||||
if (i != 0 && dcb->connector.entry[i].index ==
|
||||
dcb->connector.entry[i - 1].index)
|
||||
if (i != 0 && dcb->connector.entry[i].index2 ==
|
||||
dcb->connector.entry[i - 1].index2)
|
||||
continue;
|
||||
nouveau_connector_create(dev, &dcb->connector.entry[i]);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,32 @@
|
|||
#include "drmP.h"
|
||||
#include "drm.h"
|
||||
#include "nouveau_drv.h"
|
||||
#include "nouveau_drm.h"
|
||||
|
||||
int
|
||||
nv50_fb_init(struct drm_device *dev)
|
||||
{
|
||||
/* This is needed to get meaningful information from 100c90
|
||||
* on traps. No idea what these values mean exactly. */
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
|
||||
switch (dev_priv->chipset) {
|
||||
case 0x50:
|
||||
nv_wr32(dev, 0x100c90, 0x0707ff);
|
||||
break;
|
||||
case 0xa5:
|
||||
case 0xa8:
|
||||
nv_wr32(dev, 0x100c90, 0x0d0fff);
|
||||
break;
|
||||
default:
|
||||
nv_wr32(dev, 0x100c90, 0x1d07ff);
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
nv50_fb_takedown(struct drm_device *dev)
|
||||
{
|
||||
}
|
||||
|
|
@ -233,7 +233,7 @@ nv50_fbcon_accel_init(struct fb_info *info)
|
|||
BEGIN_RING(chan, NvSub2D, 0x0808, 3);
|
||||
OUT_RING(chan, 0);
|
||||
OUT_RING(chan, 0);
|
||||
OUT_RING(chan, 0);
|
||||
OUT_RING(chan, 1);
|
||||
BEGIN_RING(chan, NvSub2D, 0x081c, 1);
|
||||
OUT_RING(chan, 1);
|
||||
BEGIN_RING(chan, NvSub2D, 0x0840, 4);
|
||||
|
|
|
|||
|
|
@ -56,6 +56,10 @@ nv50_graph_init_intr(struct drm_device *dev)
|
|||
static void
|
||||
nv50_graph_init_regs__nv(struct drm_device *dev)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
uint32_t units = nv_rd32(dev, 0x1540);
|
||||
int i;
|
||||
|
||||
NV_DEBUG(dev, "\n");
|
||||
|
||||
nv_wr32(dev, 0x400804, 0xc0000000);
|
||||
|
|
@ -65,6 +69,20 @@ nv50_graph_init_regs__nv(struct drm_device *dev)
|
|||
nv_wr32(dev, 0x405018, 0xc0000000);
|
||||
nv_wr32(dev, 0x402000, 0xc0000000);
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
if (units & 1 << i) {
|
||||
if (dev_priv->chipset < 0xa0) {
|
||||
nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
|
||||
nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
|
||||
nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
|
||||
} else {
|
||||
nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
|
||||
nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
|
||||
nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
nv_wr32(dev, 0x400108, 0xffffffff);
|
||||
|
||||
nv_wr32(dev, 0x400824, 0x00004000);
|
||||
|
|
@ -229,10 +247,6 @@ nv50_graph_create_context(struct nouveau_channel *chan)
|
|||
nouveau_grctx_vals_load(dev, ctx);
|
||||
}
|
||||
nv_wo32(dev, ctx, 0x00000/4, chan->ramin->instance >> 12);
|
||||
if ((dev_priv->chipset & 0xf0) == 0xa0)
|
||||
nv_wo32(dev, ctx, 0x00004/4, 0x00000000);
|
||||
else
|
||||
nv_wo32(dev, ctx, 0x0011c/4, 0x00000000);
|
||||
dev_priv->engine.instmem.finish_access(dev);
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -64,6 +64,9 @@
|
|||
#define CP_FLAG_ALWAYS ((2 * 32) + 13)
|
||||
#define CP_FLAG_ALWAYS_FALSE 0
|
||||
#define CP_FLAG_ALWAYS_TRUE 1
|
||||
#define CP_FLAG_INTR ((2 * 32) + 15)
|
||||
#define CP_FLAG_INTR_NOT_PENDING 0
|
||||
#define CP_FLAG_INTR_PENDING 1
|
||||
|
||||
#define CP_CTX 0x00100000
|
||||
#define CP_CTX_COUNT 0x000f0000
|
||||
|
|
@ -214,6 +217,8 @@ nv50_grctx_init(struct nouveau_grctx *ctx)
|
|||
cp_name(ctx, cp_setup_save);
|
||||
cp_set (ctx, UNK1D, SET);
|
||||
cp_wait(ctx, STATUS, BUSY);
|
||||
cp_wait(ctx, INTR, PENDING);
|
||||
cp_bra (ctx, STATUS, BUSY, cp_setup_save);
|
||||
cp_set (ctx, UNK01, SET);
|
||||
cp_set (ctx, SWAP_DIRECTION, SAVE);
|
||||
|
||||
|
|
@ -269,7 +274,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
|
|||
int offset, base;
|
||||
uint32_t units = nv_rd32 (ctx->dev, 0x1540);
|
||||
|
||||
/* 0800 */
|
||||
/* 0800: DISPATCH */
|
||||
cp_ctx(ctx, 0x400808, 7);
|
||||
gr_def(ctx, 0x400814, 0x00000030);
|
||||
cp_ctx(ctx, 0x400834, 0x32);
|
||||
|
|
@ -300,7 +305,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
|
|||
gr_def(ctx, 0x400b20, 0x0001629d);
|
||||
}
|
||||
|
||||
/* 0C00 */
|
||||
/* 0C00: VFETCH */
|
||||
cp_ctx(ctx, 0x400c08, 0x2);
|
||||
gr_def(ctx, 0x400c08, 0x0000fe0c);
|
||||
|
||||
|
|
@ -326,7 +331,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
|
|||
cp_ctx(ctx, 0x401540, 0x5);
|
||||
gr_def(ctx, 0x401550, 0x00001018);
|
||||
|
||||
/* 1800 */
|
||||
/* 1800: STREAMOUT */
|
||||
cp_ctx(ctx, 0x401814, 0x1);
|
||||
gr_def(ctx, 0x401814, 0x000000ff);
|
||||
if (dev_priv->chipset == 0x50) {
|
||||
|
|
@ -641,7 +646,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
|
|||
if (dev_priv->chipset == 0x50)
|
||||
cp_ctx(ctx, 0x4063e0, 0x1);
|
||||
|
||||
/* 6800 */
|
||||
/* 6800: M2MF */
|
||||
if (dev_priv->chipset < 0x90) {
|
||||
cp_ctx(ctx, 0x406814, 0x2b);
|
||||
gr_def(ctx, 0x406818, 0x00000f80);
|
||||
|
|
|
|||
Loading…
Reference in New Issue