mirror of https://gitee.com/openkylin/linux.git
[ARM] 5096/2: Support Toshiba TC6393XB Mobile I/O Controller.
Add support for Toshiba TC6393XB companion chip. Currently only GPIO and part of IRQ features of the device are supported. Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Dmitry Baryshkov
Russell King
parent
b032fccca8
commit
d6315949ac
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@ -38,6 +38,12 @@ config HTC_PASIC3
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HTC Magician devices, respectively. Actual functionality is
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handled by the leds-pasic3 and ds1wm drivers.
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config MFD_TC6393XB
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bool "Support Toshiba TC6393XB"
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depends on HAVE_GPIO_LIB
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help
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Support for Toshiba Mobile IO Controller TC6393XB
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endmenu
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menu "Multimedia Capabilities Port drivers"
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@ -8,6 +8,8 @@ obj-$(CONFIG_MFD_ASIC3) += asic3.o
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obj-$(CONFIG_HTC_EGPIO) += htc-egpio.o
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obj-$(CONFIG_HTC_PASIC3) += htc-pasic3.o
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obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o
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obj-$(CONFIG_MCP) += mcp-core.o
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obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o
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obj-$(CONFIG_MCP_UCB1200) += ucb1x00-core.o
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@ -0,0 +1,537 @@
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/*
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* Toshiba TC6393XB SoC support
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*
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* Copyright(c) 2005-2006 Chris Humbert
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* Copyright(c) 2005 Dirk Opfer
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* Copyright(c) 2005 Ian Molton <spyro@f2s.com>
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* Copyright(c) 2007 Dmitry Baryshkov
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*
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* Based on code written by Sharp/Lineo for 2.4 kernels
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* Based on locomo.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/fb.h>
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#include <linux/clk.h>
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#include <linux/mfd/tc6393xb.h>
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#include <linux/gpio.h>
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#define SCR_REVID 0x08 /* b Revision ID */
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#define SCR_ISR 0x50 /* b Interrupt Status */
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#define SCR_IMR 0x52 /* b Interrupt Mask */
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#define SCR_IRR 0x54 /* b Interrupt Routing */
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#define SCR_GPER 0x60 /* w GP Enable */
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#define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
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#define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
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#define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
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#define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
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#define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
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#define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
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#define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
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#define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
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#define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
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#define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
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#define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
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#define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
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#define SCR_CCR 0x98 /* w Clock Control */
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#define SCR_PLL2CR 0x9a /* w PLL2 Control */
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#define SCR_PLL1CR 0x9c /* l PLL1 Control */
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#define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
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#define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
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#define SCR_FER 0xe0 /* b Function Enable */
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#define SCR_MCR 0xe4 /* w Mode Control */
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#define SCR_CONFIG 0xfc /* b Configuration Control */
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#define SCR_DEBUG 0xff /* b Debug */
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#define SCR_CCR_CK32K BIT(0)
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#define SCR_CCR_USBCK BIT(1)
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#define SCR_CCR_UNK1 BIT(4)
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#define SCR_CCR_MCLK_MASK (7 << 8)
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#define SCR_CCR_MCLK_OFF (0 << 8)
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#define SCR_CCR_MCLK_12 (1 << 8)
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#define SCR_CCR_MCLK_24 (2 << 8)
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#define SCR_CCR_MCLK_48 (3 << 8)
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#define SCR_CCR_HCLK_MASK (3 << 12)
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#define SCR_CCR_HCLK_24 (0 << 12)
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#define SCR_CCR_HCLK_48 (1 << 12)
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#define SCR_FER_USBEN BIT(0) /* USB host enable */
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#define SCR_FER_LCDCVEN BIT(1) /* polysilicon TFT enable */
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#define SCR_FER_SLCDEN BIT(2) /* SLCD enable */
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#define SCR_MCR_RDY_MASK (3 << 0)
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#define SCR_MCR_RDY_OPENDRAIN (0 << 0)
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#define SCR_MCR_RDY_TRISTATE (1 << 0)
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#define SCR_MCR_RDY_PUSHPULL (2 << 0)
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#define SCR_MCR_RDY_UNK BIT(2)
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#define SCR_MCR_RDY_EN BIT(3)
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#define SCR_MCR_INT_MASK (3 << 4)
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#define SCR_MCR_INT_OPENDRAIN (0 << 4)
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#define SCR_MCR_INT_TRISTATE (1 << 4)
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#define SCR_MCR_INT_PUSHPULL (2 << 4)
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#define SCR_MCR_INT_UNK BIT(6)
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#define SCR_MCR_INT_EN BIT(7)
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/* bits 8 - 16 are unknown */
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#define TC_GPIO_BIT(i) (1 << (i & 0x7))
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/*--------------------------------------------------------------------------*/
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struct tc6393xb {
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void __iomem *scr;
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struct gpio_chip gpio;
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struct clk *clk; /* 3,6 Mhz */
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spinlock_t lock; /* protects RMW cycles */
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struct {
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u8 fer;
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u16 ccr;
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u8 gpi_bcr[3];
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u8 gpo_dsr[3];
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u8 gpo_doecr[3];
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} suspend_state;
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struct resource rscr;
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struct resource *iomem;
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int irq;
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int irq_base;
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};
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/*--------------------------------------------------------------------------*/
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static int tc6393xb_gpio_get(struct gpio_chip *chip,
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unsigned offset)
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{
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struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
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/* XXX: does dsr also represent inputs? */
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return ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8))
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& TC_GPIO_BIT(offset);
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}
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static void __tc6393xb_gpio_set(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
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u8 dsr;
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dsr = ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8));
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if (value)
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dsr |= TC_GPIO_BIT(offset);
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else
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dsr &= ~TC_GPIO_BIT(offset);
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iowrite8(dsr, tc6393xb->scr + SCR_GPO_DSR(offset / 8));
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}
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static void tc6393xb_gpio_set(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
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unsigned long flags;
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spin_lock_irqsave(&tc6393xb->lock, flags);
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__tc6393xb_gpio_set(chip, offset, value);
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spin_unlock_irqrestore(&tc6393xb->lock, flags);
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}
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static int tc6393xb_gpio_direction_input(struct gpio_chip *chip,
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unsigned offset)
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{
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struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
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unsigned long flags;
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u8 doecr;
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spin_lock_irqsave(&tc6393xb->lock, flags);
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doecr = ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
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doecr &= ~TC_GPIO_BIT(offset);
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iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
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spin_unlock_irqrestore(&tc6393xb->lock, flags);
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return 0;
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}
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static int tc6393xb_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
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unsigned long flags;
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u8 doecr;
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spin_lock_irqsave(&tc6393xb->lock, flags);
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__tc6393xb_gpio_set(chip, offset, value);
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doecr = ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
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doecr |= TC_GPIO_BIT(offset);
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iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
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spin_unlock_irqrestore(&tc6393xb->lock, flags);
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return 0;
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}
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static int tc6393xb_register_gpio(struct tc6393xb *tc6393xb, int gpio_base)
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{
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tc6393xb->gpio.label = "tc6393xb";
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tc6393xb->gpio.base = gpio_base;
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tc6393xb->gpio.ngpio = 16;
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tc6393xb->gpio.set = tc6393xb_gpio_set;
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tc6393xb->gpio.get = tc6393xb_gpio_get;
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tc6393xb->gpio.direction_input = tc6393xb_gpio_direction_input;
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tc6393xb->gpio.direction_output = tc6393xb_gpio_direction_output;
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return gpiochip_add(&tc6393xb->gpio);
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}
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/*--------------------------------------------------------------------------*/
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static void
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tc6393xb_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct tc6393xb *tc6393xb = get_irq_data(irq);
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unsigned int isr;
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unsigned int i, irq_base;
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irq_base = tc6393xb->irq_base;
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while ((isr = ioread8(tc6393xb->scr + SCR_ISR) &
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~ioread8(tc6393xb->scr + SCR_IMR)))
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for (i = 0; i < TC6393XB_NR_IRQS; i++) {
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if (isr & (1 << i))
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generic_handle_irq(irq_base + i);
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}
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}
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static void tc6393xb_irq_ack(unsigned int irq)
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{
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}
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static void tc6393xb_irq_mask(unsigned int irq)
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{
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struct tc6393xb *tc6393xb = get_irq_chip_data(irq);
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unsigned long flags;
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u8 imr;
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spin_lock_irqsave(&tc6393xb->lock, flags);
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imr = ioread8(tc6393xb->scr + SCR_IMR);
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imr |= 1 << (irq - tc6393xb->irq_base);
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iowrite8(imr, tc6393xb->scr + SCR_IMR);
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spin_unlock_irqrestore(&tc6393xb->lock, flags);
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}
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static void tc6393xb_irq_unmask(unsigned int irq)
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{
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struct tc6393xb *tc6393xb = get_irq_chip_data(irq);
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unsigned long flags;
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u8 imr;
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spin_lock_irqsave(&tc6393xb->lock, flags);
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imr = ioread8(tc6393xb->scr + SCR_IMR);
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imr &= ~(1 << (irq - tc6393xb->irq_base));
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iowrite8(imr, tc6393xb->scr + SCR_IMR);
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spin_unlock_irqrestore(&tc6393xb->lock, flags);
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}
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static struct irq_chip tc6393xb_chip = {
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.name = "tc6393xb",
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.ack = tc6393xb_irq_ack,
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.mask = tc6393xb_irq_mask,
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.unmask = tc6393xb_irq_unmask,
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};
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static void tc6393xb_attach_irq(struct platform_device *dev)
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{
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struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
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unsigned int irq, irq_base;
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irq_base = tc6393xb->irq_base;
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for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
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set_irq_chip(irq, &tc6393xb_chip);
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set_irq_chip_data(irq, tc6393xb);
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set_irq_handler(irq, handle_edge_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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set_irq_type(tc6393xb->irq, IRQT_FALLING);
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set_irq_data(tc6393xb->irq, tc6393xb);
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set_irq_chained_handler(tc6393xb->irq, tc6393xb_irq);
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}
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static void tc6393xb_detach_irq(struct platform_device *dev)
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{
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struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
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unsigned int irq, irq_base;
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set_irq_chained_handler(tc6393xb->irq, NULL);
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set_irq_data(tc6393xb->irq, NULL);
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irq_base = tc6393xb->irq_base;
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for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
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set_irq_flags(irq, 0);
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set_irq_chip(irq, NULL);
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set_irq_chip_data(irq, NULL);
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}
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}
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/*--------------------------------------------------------------------------*/
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static int tc6393xb_hw_init(struct platform_device *dev)
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{
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struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
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struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
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int i;
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iowrite8(tc6393xb->suspend_state.fer, tc6393xb->scr + SCR_FER);
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iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
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iowrite16(tc6393xb->suspend_state.ccr, tc6393xb->scr + SCR_CCR);
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iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
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SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
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BIT(15), tc6393xb->scr + SCR_MCR);
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iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
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iowrite8(0, tc6393xb->scr + SCR_IRR);
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iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
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for (i = 0; i < 3; i++) {
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iowrite8(tc6393xb->suspend_state.gpo_dsr[i],
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tc6393xb->scr + SCR_GPO_DSR(i));
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iowrite8(tc6393xb->suspend_state.gpo_doecr[i],
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tc6393xb->scr + SCR_GPO_DOECR(i));
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iowrite8(tc6393xb->suspend_state.gpi_bcr[i],
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tc6393xb->scr + SCR_GPI_BCR(i));
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}
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return 0;
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}
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static int __devinit tc6393xb_probe(struct platform_device *dev)
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{
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struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
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struct tc6393xb *tc6393xb;
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struct resource *iomem;
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struct resource *rscr;
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int retval, temp;
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int i;
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iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
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if (!iomem)
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return -EINVAL;
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tc6393xb = kzalloc(sizeof *tc6393xb, GFP_KERNEL);
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if (!tc6393xb) {
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retval = -ENOMEM;
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goto err_kzalloc;
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}
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spin_lock_init(&tc6393xb->lock);
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platform_set_drvdata(dev, tc6393xb);
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tc6393xb->iomem = iomem;
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tc6393xb->irq = platform_get_irq(dev, 0);
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tc6393xb->irq_base = tcpd->irq_base;
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tc6393xb->clk = clk_get(&dev->dev, "GPIO27_CLK" /* "CK3P6MI" */);
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if (IS_ERR(tc6393xb->clk)) {
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retval = PTR_ERR(tc6393xb->clk);
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goto err_clk_get;
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}
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rscr = &tc6393xb->rscr;
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rscr->name = "tc6393xb-core";
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rscr->start = iomem->start;
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rscr->end = iomem->start + 0xff;
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rscr->flags = IORESOURCE_MEM;
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retval = request_resource(iomem, rscr);
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if (retval)
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goto err_request_scr;
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tc6393xb->scr = ioremap(rscr->start, rscr->end - rscr->start + 1);
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if (!tc6393xb->scr) {
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retval = -ENOMEM;
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goto err_ioremap;
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}
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retval = clk_enable(tc6393xb->clk);
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if (retval)
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goto err_clk_enable;
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retval = tcpd->enable(dev);
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if (retval)
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goto err_enable;
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tc6393xb->suspend_state.fer = 0;
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for (i = 0; i < 3; i++) {
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tc6393xb->suspend_state.gpo_dsr[i] =
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(tcpd->scr_gpo_dsr >> (8 * i)) & 0xff;
|
||||
tc6393xb->suspend_state.gpo_doecr[i] =
|
||||
(tcpd->scr_gpo_doecr >> (8 * i)) & 0xff;
|
||||
}
|
||||
/*
|
||||
* It may be necessary to change this back to
|
||||
* platform-dependant code
|
||||
*/
|
||||
tc6393xb->suspend_state.ccr = SCR_CCR_UNK1 |
|
||||
SCR_CCR_HCLK_48;
|
||||
|
||||
retval = tc6393xb_hw_init(dev);
|
||||
if (retval)
|
||||
goto err_hw_init;
|
||||
|
||||
printk(KERN_INFO "Toshiba tc6393xb revision %d at 0x%08lx, irq %d\n",
|
||||
ioread8(tc6393xb->scr + SCR_REVID),
|
||||
(unsigned long) iomem->start, tc6393xb->irq);
|
||||
|
||||
tc6393xb->gpio.base = -1;
|
||||
|
||||
if (tcpd->gpio_base >= 0) {
|
||||
retval = tc6393xb_register_gpio(tc6393xb, tcpd->gpio_base);
|
||||
if (retval)
|
||||
goto err_gpio_add;
|
||||
}
|
||||
|
||||
if (tc6393xb->irq)
|
||||
tc6393xb_attach_irq(dev);
|
||||
|
||||
return 0;
|
||||
|
||||
if (tc6393xb->irq)
|
||||
tc6393xb_detach_irq(dev);
|
||||
|
||||
err_gpio_add:
|
||||
if (tc6393xb->gpio.base != -1)
|
||||
temp = gpiochip_remove(&tc6393xb->gpio);
|
||||
err_hw_init:
|
||||
tcpd->disable(dev);
|
||||
err_clk_enable:
|
||||
clk_disable(tc6393xb->clk);
|
||||
err_enable:
|
||||
iounmap(tc6393xb->scr);
|
||||
err_ioremap:
|
||||
release_resource(&tc6393xb->rscr);
|
||||
err_request_scr:
|
||||
clk_put(tc6393xb->clk);
|
||||
err_clk_get:
|
||||
kfree(tc6393xb);
|
||||
err_kzalloc:
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int __devexit tc6393xb_remove(struct platform_device *dev)
|
||||
{
|
||||
struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
|
||||
struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
if (tc6393xb->irq)
|
||||
tc6393xb_detach_irq(dev);
|
||||
|
||||
if (tc6393xb->gpio.base != -1) {
|
||||
ret = gpiochip_remove(&tc6393xb->gpio);
|
||||
if (ret) {
|
||||
dev_err(&dev->dev, "Can't remove gpio chip: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
ret = tcpd->disable(dev);
|
||||
|
||||
clk_disable(tc6393xb->clk);
|
||||
|
||||
iounmap(tc6393xb->scr);
|
||||
|
||||
release_resource(&tc6393xb->rscr);
|
||||
|
||||
platform_set_drvdata(dev, NULL);
|
||||
|
||||
clk_put(tc6393xb->clk);
|
||||
|
||||
kfree(tc6393xb);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state)
|
||||
{
|
||||
struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
|
||||
struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
|
||||
int i;
|
||||
|
||||
|
||||
tc6393xb->suspend_state.ccr = ioread16(tc6393xb->scr + SCR_CCR);
|
||||
tc6393xb->suspend_state.fer = ioread8(tc6393xb->scr + SCR_FER);
|
||||
|
||||
for (i = 0; i < 3; i++) {
|
||||
tc6393xb->suspend_state.gpo_dsr[i] =
|
||||
ioread8(tc6393xb->scr + SCR_GPO_DSR(i));
|
||||
tc6393xb->suspend_state.gpo_doecr[i] =
|
||||
ioread8(tc6393xb->scr + SCR_GPO_DOECR(i));
|
||||
tc6393xb->suspend_state.gpi_bcr[i] =
|
||||
ioread8(tc6393xb->scr + SCR_GPI_BCR(i));
|
||||
}
|
||||
|
||||
return tcpd->suspend(dev);
|
||||
}
|
||||
|
||||
static int tc6393xb_resume(struct platform_device *dev)
|
||||
{
|
||||
struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
|
||||
int ret = tcpd->resume(dev);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return tc6393xb_hw_init(dev);
|
||||
}
|
||||
#else
|
||||
#define tc6393xb_suspend NULL
|
||||
#define tc6393xb_resume NULL
|
||||
#endif
|
||||
|
||||
static struct platform_driver tc6393xb_driver = {
|
||||
.probe = tc6393xb_probe,
|
||||
.remove = __devexit_p(tc6393xb_remove),
|
||||
.suspend = tc6393xb_suspend,
|
||||
.resume = tc6393xb_resume,
|
||||
|
||||
.driver = {
|
||||
.name = "tc6393xb",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init tc6393xb_init(void)
|
||||
{
|
||||
return platform_driver_register(&tc6393xb_driver);
|
||||
}
|
||||
|
||||
static void __exit tc6393xb_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&tc6393xb_driver);
|
||||
}
|
||||
|
||||
subsys_initcall(tc6393xb_init);
|
||||
module_exit(tc6393xb_exit);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov and Dirk Opfer");
|
||||
MODULE_DESCRIPTION("tc6393xb Toshiba Mobile IO Controller");
|
||||
MODULE_ALIAS("platform:tc6393xb");
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* Toshiba TC6393XB SoC support
|
||||
*
|
||||
* Copyright(c) 2005-2006 Chris Humbert
|
||||
* Copyright(c) 2005 Dirk Opfer
|
||||
* Copyright(c) 2005 Ian Molton <spyro@f2s.com>
|
||||
* Copyright(c) 2007 Dmitry Baryshkov
|
||||
*
|
||||
* Based on code written by Sharp/Lineo for 2.4 kernels
|
||||
* Based on locomo.c
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef TC6393XB_H
|
||||
#define TC6393XB_H
|
||||
|
||||
/* Also one should provide the CK3P6MI clock */
|
||||
struct tc6393xb_platform_data {
|
||||
u16 scr_pll2cr; /* PLL2 Control */
|
||||
u16 scr_gper; /* GP Enable */
|
||||
u32 scr_gpo_doecr; /* GPO Data OE Control */
|
||||
u32 scr_gpo_dsr; /* GPO Data Set */
|
||||
|
||||
int (*enable)(struct platform_device *dev);
|
||||
int (*disable)(struct platform_device *dev);
|
||||
int (*suspend)(struct platform_device *dev);
|
||||
int (*resume)(struct platform_device *dev);
|
||||
|
||||
int irq_base; /* a base for cascaded irq */
|
||||
int gpio_base;
|
||||
};
|
||||
|
||||
/*
|
||||
* Relative to irq_base
|
||||
*/
|
||||
#define IRQ_TC6393_NAND 0
|
||||
#define IRQ_TC6393_MMC 1
|
||||
#define IRQ_TC6393_OHCI 2
|
||||
#define IRQ_TC6393_SERIAL 3
|
||||
#define IRQ_TC6393_FB 4
|
||||
|
||||
#define TC6393XB_NR_IRQS 8
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue