mirror of https://gitee.com/openkylin/linux.git
drm/i915/bxt: BXT clock divider calculation
Calculate and cache clock parameters. Follow bspec algorithm for HDMI. Use precalculated values for DisplayPort linkrates. v2: (imre) - rebase against upstream crtc_state change - use the existing CHV based helper instead of handrolling the same Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Satheeshakrishna M
Daniel Vetter
parent
5ab7b0b71e
commit
d683f3bc48
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@ -1212,6 +1212,132 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
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return true;
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}
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/* bxt clock parameters */
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struct bxt_clk_div {
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uint32_t p1;
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uint32_t p2;
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uint32_t m2_int;
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uint32_t m2_frac;
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bool m2_frac_en;
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uint32_t n;
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uint32_t prop_coef;
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uint32_t int_coef;
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uint32_t gain_ctl;
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uint32_t targ_cnt;
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uint32_t lanestagger;
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};
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/* pre-calculated values for DP linkrates */
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static struct bxt_clk_div bxt_dp_clk_val[7] = {
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/* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
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/* 270 */ {4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0xd},
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/* 540 */ {2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0x18},
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/* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
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/* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
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/* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
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/* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
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};
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static bool
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bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
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struct intel_crtc_state *crtc_state,
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struct intel_encoder *intel_encoder,
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int clock)
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{
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struct intel_shared_dpll *pll;
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struct bxt_clk_div clk_div = {0};
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if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
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intel_clock_t best_clock;
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/* Calculate HDMI div */
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/*
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* FIXME: tie the following calculation into
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* i9xx_crtc_compute_clock
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*/
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if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
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DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
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clock, pipe_name(intel_crtc->pipe));
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return false;
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}
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clk_div.p1 = best_clock.p1;
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clk_div.p2 = best_clock.p2;
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WARN_ON(best_clock.m1 != 2);
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clk_div.n = best_clock.n;
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clk_div.m2_int = best_clock.m2 >> 22;
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clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
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clk_div.m2_frac_en = clk_div.m2_frac != 0;
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/* FIXME: set coef, gain, targcnt based on freq band */
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clk_div.prop_coef = 5;
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clk_div.int_coef = 11;
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clk_div.gain_ctl = 2;
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clk_div.targ_cnt = 9;
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if (clock > 270000)
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clk_div.lanestagger = 0x18;
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else if (clock > 135000)
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clk_div.lanestagger = 0x0d;
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else if (clock > 67000)
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clk_div.lanestagger = 0x07;
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else if (clock > 33000)
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clk_div.lanestagger = 0x04;
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else
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clk_div.lanestagger = 0x02;
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} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
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intel_encoder->type == INTEL_OUTPUT_EDP) {
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struct drm_encoder *encoder = &intel_encoder->base;
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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switch (intel_dp->link_bw) {
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case DP_LINK_BW_1_62:
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clk_div = bxt_dp_clk_val[0];
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break;
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case DP_LINK_BW_2_7:
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clk_div = bxt_dp_clk_val[1];
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break;
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case DP_LINK_BW_5_4:
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clk_div = bxt_dp_clk_val[2];
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break;
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default:
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clk_div = bxt_dp_clk_val[0];
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DRM_ERROR("Unknown link rate\n");
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}
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}
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crtc_state->dpll_hw_state.ebb0 =
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PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
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crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
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crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
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crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
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if (clk_div.m2_frac_en)
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crtc_state->dpll_hw_state.pll3 =
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PORT_PLL_M2_FRAC_ENABLE;
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crtc_state->dpll_hw_state.pll6 =
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clk_div.prop_coef | PORT_PLL_INT_COEFF(clk_div.int_coef);
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crtc_state->dpll_hw_state.pll6 |=
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PORT_PLL_GAIN_CTL(clk_div.gain_ctl);
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crtc_state->dpll_hw_state.pll8 = clk_div.targ_cnt;
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crtc_state->dpll_hw_state.pcsdw12 =
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LANESTAGGER_STRAP_OVRD | clk_div.lanestagger;
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pll = intel_get_shared_dpll(intel_crtc, crtc_state);
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if (pll == NULL) {
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DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
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pipe_name(intel_crtc->pipe));
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return false;
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}
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/* shared DPLL id 0 is DPLL A */
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crtc_state->ddi_pll_sel = pll->id;
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return true;
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}
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/*
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* Tries to find a *shared* PLL for the CRTC and store it in
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* intel_crtc->ddi_pll_sel.
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@ -1230,6 +1356,9 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
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if (IS_SKYLAKE(dev))
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return skl_ddi_pll_select(intel_crtc, crtc_state,
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intel_encoder, clock);
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else if (IS_BROXTON(dev))
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return bxt_ddi_pll_select(intel_crtc, crtc_state,
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intel_encoder, clock);
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else
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return hsw_ddi_pll_select(intel_crtc, crtc_state,
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intel_encoder, clock);
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