mirror of https://gitee.com/openkylin/linux.git
x86/smp/boot: Add cmdline "cpu_init_udelay=N" to specify cpu_up() delay
No change to default behavior. Replace the hard-coded mdelay(10) in cpu_up() with a variable udelay, that is set to a defined default -- rather than a magic number. Add a boot-time override, "cpu_init_udelay=N" Signed-off-by: Len Brown <len.brown@intel.com> Cc: Alan Cox <alan@linux.intel.com> Cc: Arjan van de Ven <arjan@linux.intel.com> Cc: Borislav Petkov <bp@alien8.de> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Jan H. Schönherr <jschoenh@amazon.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/2fe8e6c798e8def271122f62df9bbf58dc283e2a.1431379433.git.len.brown@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -746,6 +746,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
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cpuidle.off=1 [CPU_IDLE]
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cpuidle.off=1 [CPU_IDLE]
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disable the cpuidle sub-system
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disable the cpuidle sub-system
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cpu_init_udelay=N
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[X86] Delay for N microsec between assert and de-assert
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of APIC INIT to start processors. This delay occurs
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on every CPU online, such as boot, and resume from suspend.
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Default: 10000
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cpcihp_generic= [HW,PCI] Generic port I/O CompactPCI driver
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cpcihp_generic= [HW,PCI] Generic port I/O CompactPCI driver
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Format:
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Format:
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<first_slot>,<last_slot>,<port>,<enum_bit>[,<debug>]
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<first_slot>,<last_slot>,<port>,<enum_bit>[,<debug>]
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@ -513,6 +513,27 @@ void __inquire_remote_apic(int apicid)
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}
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}
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}
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}
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/*
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* The Multiprocessor Specification 1.4 (1997) example code suggests
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* that there should be a 10ms delay between the BSP asserting INIT
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* and de-asserting INIT, when starting a remote processor.
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* But that slows boot and resume on modern processors, which include
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* many cores and don't require that delay.
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*
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* Cmdline "init_cpu_udelay=" is available to over-ride this delay.
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*/
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#define UDELAY_10MS_DEFAULT 10000
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static unsigned int init_udelay = UDELAY_10MS_DEFAULT;
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static int __init cpu_init_udelay(char *str)
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{
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get_option(&str, &init_udelay);
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return 0;
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}
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early_param("cpu_init_udelay", cpu_init_udelay);
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/*
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/*
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* Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
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* Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
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* INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
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* INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
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@ -584,7 +605,7 @@ wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
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pr_debug("Waiting for send to finish...\n");
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pr_debug("Waiting for send to finish...\n");
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send_status = safe_apic_wait_icr_idle();
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send_status = safe_apic_wait_icr_idle();
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mdelay(10);
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mdelay(init_udelay);
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pr_debug("Deasserting INIT\n");
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pr_debug("Deasserting INIT\n");
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