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drm/tegra: sor - Do not program interlaced mode registers 

Interlaced mode is currently not supported on the SOR, so don't program
any associated registers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding 2014-06-05 16:17:25 +02:00
parent a4263fed28
commit d6922295e2
1 changed files with 0 additions and 3 deletions
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3
drivers/gpu/drm/tegra/sor.c
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@ -849,9 +849,6 @@ static int tegra_output_sor_enable(struct tegra_output *output)
value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0)); tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0));
/* XXX interlaced mode */
tegra_sor_writel(sor, 0x00000001, SOR_HEAD_STATE_5(0));
/* CSTM (LVDS, link A/B, upper) */ /* CSTM (LVDS, link A/B, upper) */
value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
SOR_CSTM_UPPER; SOR_CSTM_UPPER;