mirror of https://gitee.com/openkylin/linux.git
drm/amd/powerplay: set defalut dpm table for smu
Add smu_set_default_dpm_table function to set dpm table for smu11. Modified the sequence to populate smc pptable, as it should be done after related dpm feature is enabled. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Likun Gao
Alex Deucher
parent
e1c6f86a91
commit
d6a4aa825a
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@ -347,15 +347,6 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
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if (ret)
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return ret;
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/*
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* Set initialized values (get from vbios) to dpm tables context such as
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* gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
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* type of clks.
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*/
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ret = smu_populate_smc_pptable(smu);
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if (ret)
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return ret;
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/*
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* Send msg GetDriverIfVersion to check if the return value is equal
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* with DRIVER_IF_VERSION of smc header.
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@ -393,6 +384,15 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
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if (ret)
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return ret;
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/*
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* Set initialized values (get from vbios) to dpm tables context such as
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* gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
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* type of clks.
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*/
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ret = smu_populate_smc_pptable(smu);
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if (ret)
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return ret;
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/*
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* Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
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*/
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@ -208,6 +208,7 @@ struct pptable_funcs {
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int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index);
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int (*run_afll_btc)(struct smu_context *smu);
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int (*get_unallowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
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int (*set_default_dpm_table)(struct smu_context *smu);
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};
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struct smu_funcs
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@ -313,6 +314,8 @@ struct smu_funcs
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((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
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#define smu_append_powerplay_table(smu) \
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((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
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#define smu_set_default_dpm_table(smu) \
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((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
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#define smu_msg_get_index(smu, msg) \
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((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
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@ -525,43 +525,11 @@ static int smu_v11_0_parse_pptable(struct smu_context *smu)
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static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
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{
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struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
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int ret;
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PPTable_t *driver_ppt = (PPTable_t *)&(smu->smu_table.tables[TABLE_PPTABLE]);
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struct smu_11_0_dpm_context *dpm_context = (struct smu_11_0_dpm_context *)smu_dpm->dpm_context;
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ret = smu_set_default_dpm_table(smu);
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if (dpm_context && driver_ppt) {
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dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
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dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
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dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
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dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
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dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
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dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
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dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
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dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
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dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
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dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
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dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
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dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
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dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
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dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
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dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
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dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
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dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
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dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
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return 0;
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}
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return -EINVAL;
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return ret;
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}
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static int smu_v11_0_copy_table_to_smc(struct smu_context *smu,
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@ -291,6 +291,241 @@ vega20_get_unallowed_feature_mask(struct smu_context *smu,
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return 0;
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}
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static int
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vega20_set_single_dpm_table(struct smu_context *smu,
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struct vega20_single_dpm_table *single_dpm_table,
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PPCLK_e clk_id)
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{
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int ret = 0;
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uint32_t i, num_of_levels, clk;
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ret = smu_send_smc_msg_with_param(smu,
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SMU_MSG_GetDpmFreqByIndex,
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(clk_id << 16 | 0xFF));
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if (ret) {
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pr_err("[GetNumOfDpmLevel] failed to get dpm levels!");
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return ret;
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}
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smu_read_smc_arg(smu, &num_of_levels);
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if (!num_of_levels) {
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pr_err("[GetNumOfDpmLevel] number of clk levels is invalid!");
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return -EINVAL;
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}
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single_dpm_table->count = num_of_levels;
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for (i = 0; i < num_of_levels; i++) {
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ret = smu_send_smc_msg_with_param(smu,
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SMU_MSG_GetDpmFreqByIndex,
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(clk_id << 16 | i));
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if (ret) {
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pr_err("[GetDpmFreqByIndex] failed to get dpm freq by index!");
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return ret;
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}
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smu_read_smc_arg(smu, &clk);
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if (!clk) {
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pr_err("[GetDpmFreqByIndex] clk value is invalid!");
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return -EINVAL;
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}
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single_dpm_table->dpm_levels[i].value = clk;
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single_dpm_table->dpm_levels[i].enabled = true;
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}
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return 0;
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}
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static void vega20_init_single_dpm_state(struct vega20_dpm_state *dpm_state)
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{
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dpm_state->soft_min_level = 0x0;
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dpm_state->soft_max_level = 0xffff;
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dpm_state->hard_min_level = 0x0;
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dpm_state->hard_max_level = 0xffff;
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}
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static int vega20_set_default_dpm_table(struct smu_context *smu)
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{
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int ret;
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struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
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struct vega20_dpm_table *dpm_table = NULL;
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struct vega20_single_dpm_table *single_dpm_table;
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dpm_table = smu_dpm->dpm_context;
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/* socclk */
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single_dpm_table = &(dpm_table->soc_table);
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if (smu_feature_is_enabled(smu, FEATURE_DPM_SOCCLK_BIT)) {
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ret = vega20_set_single_dpm_table(smu, single_dpm_table,
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PPCLK_SOCCLK);
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if (ret) {
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pr_err("[SetupDefaultDpmTable] failed to get socclk dpm levels!");
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return ret;
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}
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} else {
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single_dpm_table->count = 1;
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single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
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}
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vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
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/* gfxclk */
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single_dpm_table = &(dpm_table->gfx_table);
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if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT)) {
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ret = vega20_set_single_dpm_table(smu, single_dpm_table,
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PPCLK_GFXCLK);
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if (ret) {
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pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
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return ret;
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}
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} else {
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single_dpm_table->count = 1;
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single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
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}
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vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
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/* memclk */
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single_dpm_table = &(dpm_table->mem_table);
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if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
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ret = vega20_set_single_dpm_table(smu, single_dpm_table,
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PPCLK_UCLK);
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if (ret) {
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pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
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return ret;
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}
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} else {
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single_dpm_table->count = 1;
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single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
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}
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vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
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#if 0
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/* eclk */
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single_dpm_table = &(dpm_table->eclk_table);
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if (feature->fea_enabled[FEATURE_DPM_VCE_BIT]) {
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ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_ECLK);
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if (ret) {
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pr_err("[SetupDefaultDpmTable] failed to get eclk dpm levels!");
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return ret;
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}
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} else {
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single_dpm_table->count = 1;
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single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.eclock / 100;
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}
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vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
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/* vclk */
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single_dpm_table = &(dpm_table->vclk_table);
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if (feature->fea_enabled[FEATURE_DPM_UVD_BIT]) {
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ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_VCLK);
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if (ret) {
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pr_err("[SetupDefaultDpmTable] failed to get vclk dpm levels!");
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return ret;
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}
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} else {
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single_dpm_table->count = 1;
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single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclock / 100;
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}
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vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
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/* dclk */
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single_dpm_table = &(dpm_table->dclk_table);
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if (feature->fea_enabled[FEATURE_DPM_UVD_BIT]) {
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ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_DCLK);
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if (ret) {
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pr_err("[SetupDefaultDpmTable] failed to get dclk dpm levels!");
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return ret;
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}
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} else {
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single_dpm_table->count = 1;
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single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclock / 100;
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}
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vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
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#endif
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/* dcefclk */
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single_dpm_table = &(dpm_table->dcef_table);
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if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT)) {
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ret = vega20_set_single_dpm_table(smu, single_dpm_table,
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PPCLK_DCEFCLK);
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if (ret) {
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pr_err("[SetupDefaultDpmTable] failed to get dcefclk dpm levels!");
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return ret;
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}
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} else {
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single_dpm_table->count = 1;
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single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
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}
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vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
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/* pixclk */
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single_dpm_table = &(dpm_table->pixel_table);
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if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT)) {
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ret = vega20_set_single_dpm_table(smu, single_dpm_table,
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PPCLK_PIXCLK);
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if (ret) {
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pr_err("[SetupDefaultDpmTable] failed to get pixclk dpm levels!");
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return ret;
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}
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} else {
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single_dpm_table->count = 0;
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}
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vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
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/* dispclk */
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single_dpm_table = &(dpm_table->display_table);
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if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT)) {
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ret = vega20_set_single_dpm_table(smu, single_dpm_table,
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PPCLK_DISPCLK);
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if (ret) {
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pr_err("[SetupDefaultDpmTable] failed to get dispclk dpm levels!");
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return ret;
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}
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} else {
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single_dpm_table->count = 0;
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}
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vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
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/* phyclk */
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single_dpm_table = &(dpm_table->phy_table);
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if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT)) {
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ret = vega20_set_single_dpm_table(smu, single_dpm_table,
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PPCLK_PHYCLK);
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if (ret) {
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pr_err("[SetupDefaultDpmTable] failed to get phyclk dpm levels!");
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return ret;
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}
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} else {
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single_dpm_table->count = 0;
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}
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vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
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/* fclk */
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single_dpm_table = &(dpm_table->fclk_table);
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if (smu_feature_is_enabled(smu,FEATURE_DPM_FCLK_BIT)) {
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ret = vega20_set_single_dpm_table(smu, single_dpm_table,
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PPCLK_FCLK);
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if (ret) {
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pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
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return ret;
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}
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} else {
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single_dpm_table->count = 0;
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}
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vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
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return 0;
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}
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static const struct pptable_funcs vega20_ppt_funcs = {
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.alloc_dpm_context = vega20_allocate_dpm_context,
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.store_powerplay_table = vega20_store_powerplay_table,
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@ -299,6 +534,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
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.get_smu_msg_index = vega20_get_smu_msg_index,
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.run_afll_btc = vega20_run_btc_afll,
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.get_unallowed_feature_mask = vega20_get_unallowed_feature_mask,
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.set_default_dpm_table = vega20_set_default_dpm_table,
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};
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void vega20_set_ppt_funcs(struct smu_context *smu)
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