mirror of https://gitee.com/openkylin/linux.git
ARM: integrator: delete non-devicetree boot path
The Device Tree boot path now supports everything the ATAG boot can provide, and the two are equivalent. This deletes the ATAG boot path from the Integrator/AP and Integrator/CP platforms to move them on to the future. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
50564a794d
commit
d7057e1de8
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@ -317,6 +317,7 @@ config ARCH_INTEGRATOR
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select NEED_MACH_MEMORY_H
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select PLAT_VERSATILE
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select SPARSE_IRQ
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select USE_OF
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select VERSATILE_FPGA_IRQ
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help
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Support for ARM's Integrator platform.
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@ -34,63 +34,6 @@
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#include "common.h"
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#ifdef CONFIG_ATAGS
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#define INTEGRATOR_RTC_IRQ { IRQ_RTCINT }
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#define INTEGRATOR_UART0_IRQ { IRQ_UARTINT0 }
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#define INTEGRATOR_UART1_IRQ { IRQ_UARTINT1 }
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#define KMI0_IRQ { IRQ_KMIINT0 }
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#define KMI1_IRQ { IRQ_KMIINT1 }
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static AMBA_APB_DEVICE(rtc, "rtc", 0,
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INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL);
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static AMBA_APB_DEVICE(uart0, "uart0", 0,
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INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, NULL);
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static AMBA_APB_DEVICE(uart1, "uart1", 0,
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INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, NULL);
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static AMBA_APB_DEVICE(kmi0, "kmi0", 0, KMI0_BASE, KMI0_IRQ, NULL);
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static AMBA_APB_DEVICE(kmi1, "kmi1", 0, KMI1_BASE, KMI1_IRQ, NULL);
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static struct amba_device *amba_devs[] __initdata = {
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&rtc_device,
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&uart0_device,
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&uart1_device,
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&kmi0_device,
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&kmi1_device,
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};
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int __init integrator_init(bool is_cp)
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{
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int i;
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/*
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* The Integrator/AP lacks necessary AMBA PrimeCell IDs, so we need to
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* hard-code them. The Integator/CP and forward have proper cell IDs.
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* Else we leave them undefined to the bus driver can autoprobe them.
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*/
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if (!is_cp && IS_ENABLED(CONFIG_ARCH_INTEGRATOR_AP)) {
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rtc_device.periphid = 0x00041030;
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uart0_device.periphid = 0x00041010;
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uart1_device.periphid = 0x00041010;
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kmi0_device.periphid = 0x00041050;
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kmi1_device.periphid = 0x00041050;
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uart0_device.dev.platform_data = &ap_uart_data;
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uart1_device.dev.platform_data = &ap_uart_data;
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}
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for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
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struct amba_device *d = amba_devs[i];
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amba_device_register(d, &iomem_resource);
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}
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return 0;
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}
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#endif
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static DEFINE_RAW_SPINLOCK(cm_lock);
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/**
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@ -402,8 +402,6 @@ void __init ap_init_early(void)
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{
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}
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#ifdef CONFIG_OF
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static void __init ap_of_timer_init(void)
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{
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struct device_node *node;
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@ -564,136 +562,3 @@ DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
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.restart = integrator_restart,
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.dt_compat = ap_dt_board_compat,
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MACHINE_END
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#endif
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#ifdef CONFIG_ATAGS
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/*
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* For the ATAG boot some static mappings are needed. This will
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* go away with the ATAG support down the road.
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*/
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static struct map_desc ap_io_desc_atag[] __initdata = {
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{
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.virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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},
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};
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static void __init ap_map_io_atag(void)
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{
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iotable_init(ap_io_desc_atag, ARRAY_SIZE(ap_io_desc_atag));
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ap_map_io();
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}
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/*
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* This is where non-devicetree initialization code is collected and stashed
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* for eventual deletion.
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*/
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static struct platform_device pci_v3_device = {
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.name = "pci-v3",
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.id = 0,
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};
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static struct resource cfi_flash_resource = {
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.start = INTEGRATOR_FLASH_BASE,
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.end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device cfi_flash_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &ap_flash_data,
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},
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.num_resources = 1,
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.resource = &cfi_flash_resource,
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};
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static void __init ap_timer_init(void)
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{
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struct clk *clk;
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unsigned long rate;
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clk = clk_get_sys("ap_timer", NULL);
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BUG_ON(IS_ERR(clk));
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clk_prepare_enable(clk);
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rate = clk_get_rate(clk);
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writel(0, TIMER0_VA_BASE + TIMER_CTRL);
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writel(0, TIMER1_VA_BASE + TIMER_CTRL);
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writel(0, TIMER2_VA_BASE + TIMER_CTRL);
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integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE);
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integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE,
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IRQ_TIMERINT1);
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}
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#define INTEGRATOR_SC_VALID_INT 0x003fffff
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static void __init ap_init_irq(void)
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{
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/* Disable all interrupts initially. */
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/* Do the core module ones */
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writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
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/* do the header card stuff next */
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writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
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writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
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fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
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-1, INTEGRATOR_SC_VALID_INT, NULL);
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integrator_clk_init(false);
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}
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static void __init ap_init(void)
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{
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unsigned long sc_dec;
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int i;
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platform_device_register(&pci_v3_device);
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platform_device_register(&cfi_flash_device);
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ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
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sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
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for (i = 0; i < 4; i++) {
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struct lm_device *lmdev;
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if ((sc_dec & (16 << i)) == 0)
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continue;
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lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
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if (!lmdev)
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continue;
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lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
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lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
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lmdev->resource.flags = IORESOURCE_MEM;
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lmdev->irq = IRQ_AP_EXPINT0 + i;
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lmdev->id = i;
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lm_device_register(lmdev);
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}
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integrator_init(false);
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}
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MACHINE_START(INTEGRATOR, "ARM-Integrator")
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/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
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.atag_offset = 0x100,
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.reserve = integrator_reserve,
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.map_io = ap_map_io_atag,
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.init_early = ap_init_early,
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.init_irq = ap_init_irq,
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.handle_irq = fpga_handle_irq,
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.init_time = ap_timer_init,
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.init_machine = ap_init,
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.restart = integrator_restart,
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MACHINE_END
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#endif
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@ -249,7 +249,6 @@ static void __init intcp_init_early(void)
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#endif
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}
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#ifdef CONFIG_OF
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static const struct of_device_id fpga_irq_of_match[] __initconst = {
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{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
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{ /* Sentinel */ }
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@ -354,175 +353,3 @@ DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
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.restart = integrator_restart,
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.dt_compat = intcp_dt_board_compat,
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MACHINE_END
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#endif
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#ifdef CONFIG_ATAGS
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/*
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* For the ATAG boot some static mappings are needed. This will
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* go away with the ATAG support down the road.
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*/
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static struct map_desc intcp_io_desc_atag[] __initdata = {
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{
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.virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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},
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};
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static void __init intcp_map_io_atag(void)
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{
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iotable_init(intcp_io_desc_atag, ARRAY_SIZE(intcp_io_desc_atag));
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intcp_con_base = __io_address(INTEGRATOR_CP_CTL_BASE);
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intcp_map_io();
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}
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/*
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* This is where non-devicetree initialization code is collected and stashed
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* for eventual deletion.
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*/
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#define INTCP_FLASH_SIZE SZ_32M
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static struct resource intcp_flash_resource = {
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.start = INTCP_PA_FLASH_BASE,
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.end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device intcp_flash_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &intcp_flash_data,
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},
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.num_resources = 1,
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.resource = &intcp_flash_resource,
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};
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#define INTCP_ETH_SIZE 0x10
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static struct resource smc91x_resources[] = {
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[0] = {
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.start = INTEGRATOR_CP_ETH_BASE,
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.end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_CP_ETHINT,
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.end = IRQ_CP_ETHINT,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device smc91x_device = {
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.name = "smc91x",
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.id = 0,
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.num_resources = ARRAY_SIZE(smc91x_resources),
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.resource = smc91x_resources,
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};
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static struct platform_device *intcp_devs[] __initdata = {
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&intcp_flash_device,
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&smc91x_device,
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};
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#define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40)
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#define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE)
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#define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE)
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static void __init intcp_init_irq(void)
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{
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u32 pic_mask, cic_mask, sic_mask;
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/* These masks are for the HW IRQ registers */
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pic_mask = ~((~0u) << (11 - 0));
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pic_mask |= (~((~0u) << (29 - 22))) << 22;
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cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
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sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
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/*
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* Disable all interrupt sources
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*/
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writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
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writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
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writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
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writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
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writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
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writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
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fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
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-1, pic_mask, NULL);
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fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
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-1, cic_mask, NULL);
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fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
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IRQ_CP_CPPLDINT, sic_mask, NULL);
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integrator_clk_init(true);
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}
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#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
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#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
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#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
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static void __init cp_timer_init(void)
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{
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writel(0, TIMER0_VA_BASE + TIMER_CTRL);
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writel(0, TIMER1_VA_BASE + TIMER_CTRL);
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writel(0, TIMER2_VA_BASE + TIMER_CTRL);
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sp804_clocksource_init(TIMER2_VA_BASE, "timer2");
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sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1");
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}
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#define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
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#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
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static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
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INTEGRATOR_CP_MMC_IRQS, &mmc_data);
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static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
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INTEGRATOR_CP_AACI_IRQS, NULL);
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static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
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{ IRQ_CP_CLCDCINT }, &clcd_data);
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static struct amba_device *amba_devs[] __initdata = {
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&mmc_device,
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&aaci_device,
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&clcd_device,
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};
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static void __init intcp_init(void)
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{
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int i;
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platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
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for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
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struct amba_device *d = amba_devs[i];
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amba_device_register(d, &iomem_resource);
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}
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integrator_init(true);
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}
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MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
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/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
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.atag_offset = 0x100,
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.reserve = integrator_reserve,
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.map_io = intcp_map_io_atag,
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.init_early = intcp_init_early,
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.init_irq = intcp_init_irq,
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.handle_irq = fpga_handle_irq,
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.init_time = cp_timer_init,
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.init_machine = intcp_init,
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.restart = integrator_restart,
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MACHINE_END
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#endif
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@ -809,32 +809,6 @@ static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp)
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return pci_common_swizzle(dev, pinp);
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}
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static int irq_tab[4] __initdata = {
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IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
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};
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/*
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* map the specified device/slot/pin to an IRQ. This works out such
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* that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
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*/
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static int __init pci_v3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int intnr = ((slot - 9) + (pin - 1)) & 3;
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return irq_tab[intnr];
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}
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static struct hw_pci pci_v3 __initdata = {
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.swizzle = pci_v3_swizzle,
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.setup = pci_v3_setup,
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.nr_controllers = 1,
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.ops = &pci_v3_ops,
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.preinit = pci_v3_preinit,
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.postinit = pci_v3_postinit,
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};
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#ifdef CONFIG_OF
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static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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struct of_irq oirq;
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@ -851,14 +825,36 @@ static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin)
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oirq.size);
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}
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|
||||
static int __init pci_v3_dtprobe(struct platform_device *pdev,
|
||||
struct device_node *np)
|
||||
static struct hw_pci pci_v3 __initdata = {
|
||||
.swizzle = pci_v3_swizzle,
|
||||
.setup = pci_v3_setup,
|
||||
.nr_controllers = 1,
|
||||
.ops = &pci_v3_ops,
|
||||
.preinit = pci_v3_preinit,
|
||||
.postinit = pci_v3_postinit,
|
||||
};
|
||||
|
||||
static int __init pci_v3_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct of_pci_range_parser parser;
|
||||
struct of_pci_range range;
|
||||
struct resource *res;
|
||||
int irq, ret;
|
||||
|
||||
/* Remap the Integrator system controller */
|
||||
ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
|
||||
if (!ap_syscon_base) {
|
||||
dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Device tree probe path */
|
||||
if (!np) {
|
||||
dev_err(&pdev->dev, "no device tree node for PCIv3\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (of_pci_range_parser_init(&parser, np))
|
||||
return -EINVAL;
|
||||
|
||||
|
|
@ -925,76 +921,6 @@ static int __init pci_v3_dtprobe(struct platform_device *pdev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static inline int pci_v3_dtprobe(struct platform_device *pdev,
|
||||
struct device_node *np)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static int __init pci_v3_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
int ret;
|
||||
|
||||
/* Remap the Integrator system controller */
|
||||
ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
|
||||
if (!ap_syscon_base) {
|
||||
dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Device tree probe path */
|
||||
if (np)
|
||||
return pci_v3_dtprobe(pdev, np);
|
||||
|
||||
pci_v3_base = devm_ioremap(&pdev->dev, PHYS_PCI_V3_BASE, SZ_64K);
|
||||
if (!pci_v3_base) {
|
||||
dev_err(&pdev->dev, "unable to remap PCIv3 base\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "unable to grab PCI error interrupt: %d\n",
|
||||
ret);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
conf_mem.name = "PCIv3 config";
|
||||
conf_mem.start = PHYS_PCI_CONFIG_BASE;
|
||||
conf_mem.end = PHYS_PCI_CONFIG_BASE + SZ_16M - 1;
|
||||
conf_mem.flags = IORESOURCE_MEM;
|
||||
|
||||
io_mem.name = "PCIv3 I/O";
|
||||
io_mem.start = PHYS_PCI_IO_BASE;
|
||||
io_mem.end = PHYS_PCI_IO_BASE + SZ_16M - 1;
|
||||
io_mem.flags = IORESOURCE_MEM;
|
||||
|
||||
non_mem_pci = 0x00000000;
|
||||
non_mem_pci_sz = SZ_256M;
|
||||
non_mem.name = "PCIv3 non-prefetched mem";
|
||||
non_mem.start = PHYS_PCI_MEM_BASE;
|
||||
non_mem.end = PHYS_PCI_MEM_BASE + SZ_256M - 1;
|
||||
non_mem.flags = IORESOURCE_MEM;
|
||||
|
||||
pre_mem_pci = 0x10000000;
|
||||
pre_mem_pci_sz = SZ_256M;
|
||||
pre_mem.name = "PCIv3 prefetched mem";
|
||||
pre_mem.start = PHYS_PCI_PRE_BASE + SZ_256M;
|
||||
pre_mem.end = PHYS_PCI_PRE_BASE + SZ_256M - 1;
|
||||
pre_mem.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
|
||||
|
||||
pci_v3.map_irq = pci_v3_map_irq;
|
||||
|
||||
pci_common_init_dev(&pdev->dev, &pci_v3);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id pci_ids[] = {
|
||||
{ .compatible = "v3,v360epc-pci", },
|
||||
{},
|
||||
|
|
|
|||
Loading…
Reference in New Issue