mirror of https://gitee.com/openkylin/linux.git
Merge series "ASoC: SOF: DSP core management fixes for 5.10" from Kai Vehmanen <kai.vehmanen@linux.intel.com>:
This series contains some improvements to how DSP core management is done in SOF, and adds a distinction between cores managed by the host versus cores managed by the DSP. Pierre-Louis Bossart (1): ASoC: SOF: Intel: hda-loader: s/master/primary Ranjani Sridharan (3): ASoC: SOF: rename cores_mask to host_managed_cores_mask ASoC: SOF: Intel: hda: modify core_power_up/down op ASoC: SOF: Intel: remove the HDA_DSP_CORE_MASK() macro sound/soc/sof/intel/apl.c | 2 +- sound/soc/sof/intel/bdw.c | 2 +- sound/soc/sof/intel/byt.c | 6 +++--- sound/soc/sof/intel/cnl.c | 15 ++++----------- sound/soc/sof/intel/hda-dsp.c | 20 +++++++++++++++++--- sound/soc/sof/intel/hda-loader.c | 11 +++++------ sound/soc/sof/intel/hda.c | 2 +- sound/soc/sof/intel/hda.h | 3 --- sound/soc/sof/intel/shim.h | 2 +- sound/soc/sof/intel/tgl.c | 2 +- 10 files changed, 34 insertions(+), 31 deletions(-) -- 2.27.0
This commit is contained in:
Mark Brown
commit
d70a4412e2
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@ -129,7 +129,7 @@ const struct sof_intel_dsp_desc apl_chip_info = {
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/* Apollolake */
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.cores_num = 2,
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.init_core_mask = 1,
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.cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1),
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.host_managed_cores_mask = GENMASK(1, 0),
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.ipc_req = HDA_DSP_REG_HIPCI,
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.ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
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.ipc_ack = HDA_DSP_REG_HIPCIE,
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@ -655,7 +655,7 @@ EXPORT_SYMBOL_NS(sof_bdw_ops, SND_SOC_SOF_BROADWELL);
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const struct sof_intel_dsp_desc bdw_chip_info = {
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.cores_num = 1,
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.cores_mask = 1,
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.host_managed_cores_mask = 1,
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};
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EXPORT_SYMBOL_NS(bdw_chip_info, SND_SOC_SOF_BROADWELL);
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@ -651,7 +651,7 @@ EXPORT_SYMBOL_NS(sof_tng_ops, SND_SOC_SOF_MERRIFIELD);
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const struct sof_intel_dsp_desc tng_chip_info = {
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.cores_num = 1,
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.cores_mask = 1,
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.host_managed_cores_mask = 1,
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};
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EXPORT_SYMBOL_NS(tng_chip_info, SND_SOC_SOF_MERRIFIELD);
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@ -896,7 +896,7 @@ EXPORT_SYMBOL_NS(sof_byt_ops, SND_SOC_SOF_BAYTRAIL);
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const struct sof_intel_dsp_desc byt_chip_info = {
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.cores_num = 1,
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.cores_mask = 1,
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.host_managed_cores_mask = 1,
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};
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EXPORT_SYMBOL_NS(byt_chip_info, SND_SOC_SOF_BAYTRAIL);
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@ -976,7 +976,7 @@ EXPORT_SYMBOL_NS(sof_cht_ops, SND_SOC_SOF_BAYTRAIL);
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const struct sof_intel_dsp_desc cht_chip_info = {
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.cores_num = 1,
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.cores_mask = 1,
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.host_managed_cores_mask = 1,
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};
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EXPORT_SYMBOL_NS(cht_chip_info, SND_SOC_SOF_BAYTRAIL);
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@ -334,10 +334,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
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/* Cannonlake */
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.cores_num = 4,
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.init_core_mask = 1,
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.cores_mask = HDA_DSP_CORE_MASK(0) |
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HDA_DSP_CORE_MASK(1) |
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HDA_DSP_CORE_MASK(2) |
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HDA_DSP_CORE_MASK(3),
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.host_managed_cores_mask = GENMASK(3, 0),
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.ipc_req = CNL_DSP_REG_HIPCIDR,
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
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.ipc_ack = CNL_DSP_REG_HIPCIDA,
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@ -353,10 +350,7 @@ const struct sof_intel_dsp_desc icl_chip_info = {
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/* Icelake */
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.cores_num = 4,
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.init_core_mask = 1,
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.cores_mask = HDA_DSP_CORE_MASK(0) |
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HDA_DSP_CORE_MASK(1) |
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HDA_DSP_CORE_MASK(2) |
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HDA_DSP_CORE_MASK(3),
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.host_managed_cores_mask = GENMASK(3, 0),
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.ipc_req = CNL_DSP_REG_HIPCIDR,
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
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.ipc_ack = CNL_DSP_REG_HIPCIDA,
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@ -372,7 +366,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
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/* Elkhartlake */
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.cores_num = 4,
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.init_core_mask = 1,
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.cores_mask = HDA_DSP_CORE_MASK(0),
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.host_managed_cores_mask = BIT(0),
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.ipc_req = CNL_DSP_REG_HIPCIDR,
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
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.ipc_ack = CNL_DSP_REG_HIPCIDA,
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@ -388,8 +382,7 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
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/* Jasperlake */
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.cores_num = 2,
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.init_core_mask = 1,
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.cores_mask = HDA_DSP_CORE_MASK(0) |
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HDA_DSP_CORE_MASK(1),
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.host_managed_cores_mask = GENMASK(1, 0),
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.ipc_req = CNL_DSP_REG_HIPCIDR,
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
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.ipc_ack = CNL_DSP_REG_HIPCIDA,
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@ -239,10 +239,15 @@ bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
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int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
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{
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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const struct sof_intel_dsp_desc *chip = hda->desc;
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int ret;
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/* return if core is already enabled */
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if (hda_dsp_core_is_enabled(sdev, core_mask))
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/* restrict core_mask to host managed cores mask */
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core_mask &= chip->host_managed_cores_mask;
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/* return if core_mask is not valid or cores are already enabled */
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if (!core_mask || hda_dsp_core_is_enabled(sdev, core_mask))
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return 0;
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/* power up */
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@ -259,8 +264,17 @@ int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
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int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
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unsigned int core_mask)
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{
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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const struct sof_intel_dsp_desc *chip = hda->desc;
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int ret;
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/* restrict core_mask to host managed cores mask */
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core_mask &= chip->host_managed_cores_mask;
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/* return if core_mask is not valid */
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if (!core_mask)
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return 0;
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/* place core in reset prior to power down */
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ret = hda_dsp_core_stall_reset(sdev, core_mask);
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if (ret < 0) {
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@ -610,7 +624,7 @@ static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
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#endif
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/* power down DSP */
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ret = hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
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ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
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if (ret < 0) {
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dev_err(sdev->dev,
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"error: failed to power down core during suspend\n");
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@ -91,7 +91,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration)
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int i;
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/* step 1: power up corex */
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ret = hda_dsp_core_power_up(sdev, chip->cores_mask);
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ret = hda_dsp_core_power_up(sdev, chip->host_managed_cores_mask);
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if (ret < 0) {
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if (iteration == HDA_FW_BOOT_ATTEMPTS)
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dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
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@ -114,7 +114,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration)
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((stream_tag - 1) << 9)));
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/* step 3: unset core 0 reset state & unstall/run core 0 */
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ret = hda_dsp_core_run(sdev, HDA_DSP_CORE_MASK(0));
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ret = hda_dsp_core_run(sdev, BIT(0));
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if (ret < 0) {
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if (iteration == HDA_FW_BOOT_ATTEMPTS)
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dev_err(sdev->dev,
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@ -146,8 +146,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration)
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chip->ipc_ack_mask);
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/* step 5: power down corex */
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ret = hda_dsp_core_power_down(sdev,
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chip->cores_mask & ~(HDA_DSP_CORE_MASK(0)));
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ret = hda_dsp_core_power_down(sdev, chip->host_managed_cores_mask & ~(BIT(0)));
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if (ret < 0) {
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if (iteration == HDA_FW_BOOT_ATTEMPTS)
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dev_err(sdev->dev,
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@ -176,7 +175,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration)
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err:
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hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
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hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
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hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
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return ret;
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}
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@ -427,7 +426,7 @@ int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
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}
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/*
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* return master core id if both fw copy
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* return primary core id if both fw copy
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* and stream clean up are successful
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*/
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if (!ret)
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@ -928,7 +928,7 @@ int hda_dsp_remove(struct snd_sof_dev *sdev)
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/* disable cores */
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if (chip)
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hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
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hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
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/* disable DSP */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
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@ -305,9 +305,6 @@
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#define HDA_DSP_ADSPCS_CPA_SHIFT 24
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#define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
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/* Mask for a given core index, c = 0.. number of supported cores - 1 */
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#define HDA_DSP_CORE_MASK(c) BIT(c)
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/*
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* Mask for a given number of cores
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* nc = number of supported cores
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@ -154,7 +154,7 @@
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/* DSP hardware descriptor */
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struct sof_intel_dsp_desc {
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int cores_num;
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int cores_mask;
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int host_managed_cores_mask;
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int init_core_mask; /* cores available after fw boot */
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int ipc_req;
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int ipc_req_mask;
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@ -124,7 +124,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
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/* Tigerlake */
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.cores_num = 4,
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.init_core_mask = 1,
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.cores_mask = HDA_DSP_CORE_MASK(0),
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.host_managed_cores_mask = BIT(0),
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.ipc_req = CNL_DSP_REG_HIPCIDR,
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
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.ipc_ack = CNL_DSP_REG_HIPCIDA,
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