mirror of https://gitee.com/openkylin/linux.git
locking/pvqspinlock, x86: Optimize the PV unlock code path
The unlock function in queued spinlocks was optimized for better
performance on bare metal systems at the expense of virtualized guests.
For x86-64 systems, the unlock call needs to go through a
PV_CALLEE_SAVE_REGS_THUNK() which saves and restores 8 64-bit
registers before calling the real __pv_queued_spin_unlock()
function. The thunk code may also be in a separate cacheline from
__pv_queued_spin_unlock().
This patch optimizes the PV unlock code path by:
1) Moving the unlock slowpath code from the fastpath into a separate
__pv_queued_spin_unlock_slowpath() function to make the fastpath
as simple as possible..
2) For x86-64, hand-coded an assembly function to combine the register
saving thunk code with the fastpath code. Only registers that
are used in the fastpath will be saved and restored. If the
fastpath fails, the slowpath function will be called via another
PV_CALLEE_SAVE_REGS_THUNK(). For 32-bit, it falls back to the C
__pv_queued_spin_unlock() code as the thunk saves and restores
only one 32-bit register.
With a microbenchmark of 5M lock-unlock loop, the table below shows
the execution times before and after the patch with different number
of threads in a VM running on a 32-core Westmere-EX box with x86-64
4.2-rc1 based kernels:
Threads Before patch After patch % Change
------- ------------ ----------- --------
1 134.1 ms 119.3 ms -11%
2 1286 ms 953 ms -26%
3 3715 ms 3480 ms -6.3%
4 4092 ms 3764 ms -8.0%
Signed-off-by: Waiman Long <Waiman.Long@hpe.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: Douglas Hatch <doug.hatch@hpe.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Scott J Norton <scott.norton@hpe.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1447114167-47185-5-git-send-email-Waiman.Long@hpe.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Waiman Long
Ingo Molnar
parent
aa68744f80
commit
d78045306c
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@ -1,6 +1,65 @@
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#ifndef __ASM_QSPINLOCK_PARAVIRT_H
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#define __ASM_QSPINLOCK_PARAVIRT_H
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/*
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* For x86-64, PV_CALLEE_SAVE_REGS_THUNK() saves and restores 8 64-bit
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* registers. For i386, however, only 1 32-bit register needs to be saved
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* and restored. So an optimized version of __pv_queued_spin_unlock() is
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* hand-coded for 64-bit, but it isn't worthwhile to do it for 32-bit.
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*/
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#ifdef CONFIG_64BIT
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PV_CALLEE_SAVE_REGS_THUNK(__pv_queued_spin_unlock_slowpath);
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#define __pv_queued_spin_unlock __pv_queued_spin_unlock
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#define PV_UNLOCK "__raw_callee_save___pv_queued_spin_unlock"
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#define PV_UNLOCK_SLOWPATH "__raw_callee_save___pv_queued_spin_unlock_slowpath"
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/*
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* Optimized assembly version of __raw_callee_save___pv_queued_spin_unlock
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* which combines the registers saving trunk and the body of the following
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* C code:
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*
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* void __pv_queued_spin_unlock(struct qspinlock *lock)
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* {
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* struct __qspinlock *l = (void *)lock;
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* u8 lockval = cmpxchg(&l->locked, _Q_LOCKED_VAL, 0);
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*
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* if (likely(lockval == _Q_LOCKED_VAL))
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* return;
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* pv_queued_spin_unlock_slowpath(lock, lockval);
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* }
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*
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* For x86-64,
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* rdi = lock (first argument)
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* rsi = lockval (second argument)
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* rdx = internal variable (set to 0)
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*/
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asm (".pushsection .text;"
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".globl " PV_UNLOCK ";"
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".align 4,0x90;"
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PV_UNLOCK ": "
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"push %rdx;"
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"mov $0x1,%eax;"
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"xor %edx,%edx;"
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"lock cmpxchg %dl,(%rdi);"
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"cmp $0x1,%al;"
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"jne .slowpath;"
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"pop %rdx;"
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"ret;"
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".slowpath: "
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"push %rsi;"
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"movzbl %al,%esi;"
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"call " PV_UNLOCK_SLOWPATH ";"
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"pop %rsi;"
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"pop %rdx;"
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"ret;"
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".size " PV_UNLOCK ", .-" PV_UNLOCK ";"
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".popsection");
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#else /* CONFIG_64BIT */
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extern void __pv_queued_spin_unlock(struct qspinlock *lock);
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PV_CALLEE_SAVE_REGS_THUNK(__pv_queued_spin_unlock);
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#endif /* CONFIG_64BIT */
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#endif
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@ -308,23 +308,14 @@ static void pv_wait_head(struct qspinlock *lock, struct mcs_spinlock *node)
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}
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/*
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* PV version of the unlock function to be used in stead of
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* queued_spin_unlock().
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* PV versions of the unlock fastpath and slowpath functions to be used
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* instead of queued_spin_unlock().
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*/
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__visible void __pv_queued_spin_unlock(struct qspinlock *lock)
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__visible void
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__pv_queued_spin_unlock_slowpath(struct qspinlock *lock, u8 locked)
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{
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struct __qspinlock *l = (void *)lock;
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struct pv_node *node;
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u8 locked;
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/*
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* We must not unlock if SLOW, because in that case we must first
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* unhash. Otherwise it would be possible to have multiple @lock
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* entries, which would be BAD.
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*/
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locked = cmpxchg(&l->locked, _Q_LOCKED_VAL, 0);
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if (likely(locked == _Q_LOCKED_VAL))
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return;
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if (unlikely(locked != _Q_SLOW_VAL)) {
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WARN(!debug_locks_silent,
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@ -363,12 +354,32 @@ __visible void __pv_queued_spin_unlock(struct qspinlock *lock)
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*/
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pv_kick(node->cpu);
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}
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/*
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* Include the architecture specific callee-save thunk of the
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* __pv_queued_spin_unlock(). This thunk is put together with
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* __pv_queued_spin_unlock() near the top of the file to make sure
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* that the callee-save thunk and the real unlock function are close
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* to each other sharing consecutive instruction cachelines.
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* __pv_queued_spin_unlock() to make the callee-save thunk and the real unlock
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* function close to each other sharing consecutive instruction cachelines.
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* Alternatively, architecture specific version of __pv_queued_spin_unlock()
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* can be defined.
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*/
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#include <asm/qspinlock_paravirt.h>
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#ifndef __pv_queued_spin_unlock
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__visible void __pv_queued_spin_unlock(struct qspinlock *lock)
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{
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struct __qspinlock *l = (void *)lock;
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u8 locked;
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/*
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* We must not unlock if SLOW, because in that case we must first
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* unhash. Otherwise it would be possible to have multiple @lock
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* entries, which would be BAD.
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*/
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locked = cmpxchg(&l->locked, _Q_LOCKED_VAL, 0);
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if (likely(locked == _Q_LOCKED_VAL))
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return;
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__pv_queued_spin_unlock_slowpath(lock, locked);
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}
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#endif /* __pv_queued_spin_unlock */
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