mirror of https://gitee.com/openkylin/linux.git
First batch of cleanup for 4.2:
- use syscon in the ata and cf drivers to configure the SMC and drop sam9_smc.c - switch the at91rm9200 memory controller to syscon - remove last useless headers - remove now useless Makefile.boot -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJVXkSpAAoJEKbNnwlvZCyzauwQAMw7hS1F13piSpN5JBlST6yx I4ojH/wB5GzI+qvTTcBZQR0AGcDatU3cHuzIPzYypKTB76iLf5DaZPvPjN3S3EK0 2/4R2eJyz0pA/2liTQ17e0MjKSIR0Ui7kk/aWYnC92/p2KK8xpUsbxznAIkAdw8I a1HgsM1IKPVnyyxgvrKNhNcsP7fCzfjgnRNmRiFe9iDIbLervE+jKpm7PTakWtQL OeLqRoURVd7yOLeqhlrmgch0ut8MqdHPgD57M/xbgi11VSg1PwLWTpuUlbnbVFwD nw8A7d24+rUYLgyhTj92RmSiPjFyztHL6S+rw4yzaDLHMIr4Vm/U4eS9xcRhXzhe FaigePDKYQiDNZ3u3NCDwOJk3HLlTkpvlzmVd1nFn313afFOy4AtIwtyUgg51946 HkZQSU0JIcqd6y53EFjSMjdGxuDavyrYsV9KNDh3dFNHEKfe41LJBnYB9Q3mSYZC H66sqs+5JVguwNdLJKXKvrehTF0dmsawvd0cjZgBDDj8JORjBPLIquU+IVJ1isYV KDH4JjEWYqVk86j0Cpt0A+vCBOCAS21dn5wb6vi8dD4agoRr7HuQnSMbvzDhNLnY 93Ah82q5bQJjvWgb5FXYp2Ar9IhLBZ7sLqcnF1Fo5S7KCC6wMnd11/NeFYsnKfE/ N55fXpd/pPYDNg3XDs+q =iSye -----END PGP SIGNATURE----- Merge tag 'at91-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux into next/cleanup Merge "First batch of cleanup for 4.2" from Alexandre Belloni: - use syscon in the ata and cf drivers to configure the SMC and drop sam9_smc.c - switch the at91rm9200 memory controller to syscon - remove last useless headers - remove now useless Makefile.boot * tag 'at91-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: ARM: at91: remove useless Makefile.boot ARM: at91: remove at91rm9200_sdramc.h ARM: at91: remove mach/at91_ramc.h and mach/at91rm9200_mc.h ARM: at91/pm: use the atmel-mc syscon defines pcmcia: at91_cf: Use syscon to configure the MC/smc ARM: at91: declare the at91rm9200 memory controller as a syscon mfd: syscon: Add Atmel MC (Memory Controller) registers definition ARM: at91: drop sam9_smc.c ata: at91: use syscon to configure the smc
This commit is contained in:
Arnd Bergmann
commit
d7c82daf4f
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@ -98,7 +98,7 @@ Example:
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};
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RAMC SDRAM/DDR Controller required properties:
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- compatible: Should be "atmel,at91rm9200-sdramc",
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- compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
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"atmel,at91sam9260-sdramc",
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"atmel,at91sam9g45-ddramc",
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"atmel,sama5d3-ddramc",
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|
|
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@ -92,7 +92,7 @@ aic: interrupt-controller@fffff000 {
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};
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ramc0: ramc@ffffff00 {
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compatible = "atmel,at91rm9200-sdramc";
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compatible = "atmel,at91rm9200-sdramc", "syscon";
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reg = <0xffffff00 0x100>;
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};
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@ -1,13 +1,8 @@
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#
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# Makefile for the linux kernel.
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#
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ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
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asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
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obj-y := soc.o
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obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
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# CPU-specific support
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obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o
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obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o
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@ -1,8 +0,0 @@
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# Note: the following conditions must always be true:
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# ZRELADDR == virt_to_phys(TEXTADDR)
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# PARAMS_PHYS must be within 4MB of ZRELADDR
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# INITRD_PHYS must be in RAM
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zreladdr-y += 0x20008000
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params_phys-y := 0x20000100
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initrd_phys-y := 0x20410000
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@ -1,28 +0,0 @@
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/*
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* Header file for the Atmel RAM Controller
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*
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* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* Under GPLv2 only
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*/
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#ifndef __AT91_RAMC_H__
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#define __AT91_RAMC_H__
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#ifndef __ASSEMBLY__
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extern void __iomem *at91_ramc_base[];
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#define at91_ramc_read(id, field) \
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__raw_readl(at91_ramc_base[id] + field)
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#define at91_ramc_write(id, field, value) \
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__raw_writel(value, at91_ramc_base[id] + field)
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#else
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.extern at91_ramc_base
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#endif
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#include <soc/at91/at91rm9200_sdramc.h>
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#include <soc/at91/at91sam9_ddrsdr.h>
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#include <soc/at91/at91sam9_sdramc.h>
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#endif /* __AT91_RAMC_H__ */
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@ -1,116 +0,0 @@
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/*
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* arch/arm/mach-at91/include/mach/at91rm9200_mc.h
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91RM9200_MC_H
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#define AT91RM9200_MC_H
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/* Memory Controller */
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#define AT91_MC_RCR 0x00 /* MC Remap Control Register */
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#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
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#define AT91_MC_ASR 0x04 /* MC Abort Status Register */
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#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
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#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
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#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
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#define AT91_MC_ABTSZ_BYTE (0 << 8)
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#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
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#define AT91_MC_ABTSZ_WORD (2 << 8)
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#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
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#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
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#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
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#define AT91_MC_ABTTYP_FETCH (2 << 10)
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#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
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#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
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#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
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#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
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#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
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#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
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#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
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#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
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#define AT91_MC_AASR 0x08 /* MC Abort Address Status Register */
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#define AT91_MC_MPR 0x0c /* MC Master Priority Register */
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#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
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#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
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#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
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#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
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/* External Bus Interface (EBI) registers */
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#define AT91_EBI_CSA 0x60 /* Chip Select Assignment Register */
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#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
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#define AT91_EBI_CS0A_SMC (0 << 0)
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#define AT91_EBI_CS0A_BFC (1 << 0)
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#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
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#define AT91_EBI_CS1A_SMC (0 << 1)
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#define AT91_EBI_CS1A_SDRAMC (1 << 1)
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#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
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#define AT91_EBI_CS3A_SMC (0 << 3)
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#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
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#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
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#define AT91_EBI_CS4A_SMC (0 << 4)
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#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
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#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
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#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
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/* Static Memory Controller (SMC) registers */
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#define AT91_SMC_CSR(n) (0x70 + ((n) * 4)) /* SMC Chip Select Register */
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#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
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#define AT91_SMC_NWS_(x) ((x) << 0)
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#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
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#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
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#define AT91_SMC_TDF_(x) ((x) << 8)
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#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
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#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
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#define AT91_SMC_DBW_16 (1 << 13)
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#define AT91_SMC_DBW_8 (2 << 13)
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#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
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#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
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#define AT91_SMC_ACSS_STD (0 << 16)
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#define AT91_SMC_ACSS_1 (1 << 16)
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#define AT91_SMC_ACSS_2 (2 << 16)
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#define AT91_SMC_ACSS_3 (3 << 16)
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#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
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#define AT91_SMC_RWSETUP_(x) ((x) << 24)
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#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
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#define AT91_SMC_RWHOLD_(x) ((x) << 28)
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/* Burst Flash Controller register */
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#define AT91_BFC_MR 0xc0 /* Mode Register */
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#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
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#define AT91_BFC_BFCOM_DISABLED (0 << 0)
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#define AT91_BFC_BFCOM_ASYNC (1 << 0)
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#define AT91_BFC_BFCOM_BURST (2 << 0)
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#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
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#define AT91_BFC_BFCC_MCK (1 << 2)
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#define AT91_BFC_BFCC_DIV2 (2 << 2)
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#define AT91_BFC_BFCC_DIV4 (3 << 2)
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#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
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#define AT91_BFC_PAGES (7 << 8) /* Page Size */
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#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
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#define AT91_BFC_PAGES_16 (1 << 8)
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#define AT91_BFC_PAGES_32 (2 << 8)
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#define AT91_BFC_PAGES_64 (3 << 8)
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#define AT91_BFC_PAGES_128 (4 << 8)
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#define AT91_BFC_PAGES_256 (5 << 8)
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#define AT91_BFC_PAGES_512 (6 << 8)
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#define AT91_BFC_PAGES_1024 (7 << 8)
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#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
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#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
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#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
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#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
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#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
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#endif
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@ -1,98 +0,0 @@
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/*
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* arch/arm/mach-at91/include/mach/at91sam9_smc.h
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*
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* Copyright (C) 2007 Andrew Victor
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* Copyright (C) 2007 Atmel Corporation.
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*
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* Static Memory Controllers (SMC) - System peripherals registers.
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||||
* Based on AT91SAM9261 datasheet revision D.
|
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*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
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#ifndef AT91SAM9_SMC_H
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#define AT91SAM9_SMC_H
|
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|
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#ifndef __ASSEMBLY__
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struct sam9_smc_config {
|
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/* Setup register */
|
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u8 ncs_read_setup;
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u8 nrd_setup;
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u8 ncs_write_setup;
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u8 nwe_setup;
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/* Pulse register */
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u8 ncs_read_pulse;
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u8 nrd_pulse;
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u8 ncs_write_pulse;
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u8 nwe_pulse;
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/* Cycle register */
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u16 read_cycle;
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||||
u16 write_cycle;
|
||||
|
||||
/* Mode register */
|
||||
u32 mode;
|
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u8 tdf_cycles:4;
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||||
};
|
||||
|
||||
extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
|
||||
extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config);
|
||||
extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config);
|
||||
extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
|
||||
#endif
|
||||
|
||||
#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */
|
||||
#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
|
||||
#define AT91_SMC_NWESETUP_(x) ((x) << 0)
|
||||
#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
|
||||
#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
|
||||
#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
|
||||
#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
|
||||
#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
|
||||
#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
|
||||
|
||||
#define AT91_SMC_PULSE 0x04 /* Pulse Register for CS n */
|
||||
#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
|
||||
#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
|
||||
#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
|
||||
#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
|
||||
#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
|
||||
#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
|
||||
#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
|
||||
#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
|
||||
|
||||
#define AT91_SMC_CYCLE 0x08 /* Cycle Register for CS n */
|
||||
#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
|
||||
#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
|
||||
#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
|
||||
#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
|
||||
|
||||
#define AT91_SMC_MODE 0x0c /* Mode Register for CS n */
|
||||
#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
|
||||
#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
|
||||
#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
|
||||
#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
|
||||
#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
|
||||
#define AT91_SMC_EXNWMODE_READY (3 << 4)
|
||||
#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
|
||||
#define AT91_SMC_BAT_SELECT (0 << 8)
|
||||
#define AT91_SMC_BAT_WRITE (1 << 8)
|
||||
#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
|
||||
#define AT91_SMC_DBW_8 (0 << 12)
|
||||
#define AT91_SMC_DBW_16 (1 << 12)
|
||||
#define AT91_SMC_DBW_32 (2 << 12)
|
||||
#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
|
||||
#define AT91_SMC_TDF_(x) ((x) << 16)
|
||||
#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
|
||||
#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
|
||||
#define AT91_SMC_PS (3 << 28) /* Page Size */
|
||||
#define AT91_SMC_PS_4 (0 << 28)
|
||||
#define AT91_SMC_PS_8 (1 << 28)
|
||||
#define AT91_SMC_PS_16 (2 << 28)
|
||||
#define AT91_SMC_PS_32 (3 << 28)
|
||||
|
||||
#endif
|
||||
|
|
@ -233,7 +233,7 @@ static void at91_pm_set_standby(void (*at91_standby)(void))
|
|||
*/
|
||||
static void at91rm9200_standby(void)
|
||||
{
|
||||
u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
|
||||
u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR);
|
||||
|
||||
asm volatile(
|
||||
"b 1f\n\t"
|
||||
|
|
@ -244,8 +244,8 @@ static void at91rm9200_standby(void)
|
|||
" mcr p15, 0, %0, c7, c0, 4\n\t"
|
||||
" str %5, [%1, %2]"
|
||||
:
|
||||
: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
|
||||
"r" (1), "r" (AT91RM9200_SDRAMC_SRR),
|
||||
: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_MC_SDRAMC_LPR),
|
||||
"r" (1), "r" (AT91_MC_SDRAMC_SRR),
|
||||
"r" (lpr));
|
||||
}
|
||||
|
||||
|
|
@ -414,7 +414,7 @@ void __init at91rm9200_pm_init(void)
|
|||
/*
|
||||
* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
|
||||
*/
|
||||
at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
|
||||
at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
|
||||
|
||||
at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
|
||||
at91_pm_data.memctrl = AT91_MEMCTRL_MC;
|
||||
|
|
|
|||
|
|
@ -13,7 +13,19 @@
|
|||
|
||||
#include <asm/proc-fns.h>
|
||||
|
||||
#include <mach/at91_ramc.h>
|
||||
#include <linux/mfd/syscon/atmel-mc.h>
|
||||
#include <soc/at91/at91sam9_ddrsdr.h>
|
||||
#include <soc/at91/at91sam9_sdramc.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void __iomem *at91_ramc_base[];
|
||||
|
||||
#define at91_ramc_read(id, field) \
|
||||
__raw_readl(at91_ramc_base[id] + field)
|
||||
|
||||
#define at91_ramc_write(id, field, value) \
|
||||
__raw_writel(value, at91_ramc_base[id] + field)
|
||||
#endif
|
||||
|
||||
#define AT91_MEMCTRL_MC 0
|
||||
#define AT91_MEMCTRL_SDRAMC 1
|
||||
|
|
|
|||
|
|
@ -13,7 +13,6 @@
|
|||
*/
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/clk/at91_pmc.h>
|
||||
#include <mach/at91_ramc.h>
|
||||
#include "pm.h"
|
||||
|
||||
#define SRAMC_SELF_FRESH_ACTIVE 0x01
|
||||
|
|
@ -216,7 +215,7 @@ ENTRY(at91_sramc_self_refresh)
|
|||
|
||||
/* Active SDRAM self-refresh mode */
|
||||
mov r3, #1
|
||||
str r3, [r2, #AT91RM9200_SDRAMC_SRR]
|
||||
str r3, [r2, #AT91_MC_SDRAMC_SRR]
|
||||
b exit_sramc_sf
|
||||
|
||||
ddrc_sf:
|
||||
|
|
|
|||
|
|
@ -1,136 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-at91/sam9_smc.c
|
||||
*
|
||||
* Copyright (C) 2008 Andrew Victor
|
||||
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include <mach/at91sam9_smc.h>
|
||||
|
||||
#include "sam9_smc.h"
|
||||
|
||||
|
||||
#define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * 0x10))
|
||||
|
||||
static void __iomem *smc_base_addr[2];
|
||||
|
||||
static void sam9_smc_cs_write_mode(void __iomem *base,
|
||||
struct sam9_smc_config *config)
|
||||
{
|
||||
__raw_writel(config->mode
|
||||
| AT91_SMC_TDF_(config->tdf_cycles),
|
||||
base + AT91_SMC_MODE);
|
||||
}
|
||||
|
||||
void sam9_smc_write_mode(int id, int cs,
|
||||
struct sam9_smc_config *config)
|
||||
{
|
||||
sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(sam9_smc_write_mode);
|
||||
|
||||
static void sam9_smc_cs_configure(void __iomem *base,
|
||||
struct sam9_smc_config *config)
|
||||
{
|
||||
|
||||
/* Setup register */
|
||||
__raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup)
|
||||
| AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
|
||||
| AT91_SMC_NRDSETUP_(config->nrd_setup)
|
||||
| AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup),
|
||||
base + AT91_SMC_SETUP);
|
||||
|
||||
/* Pulse register */
|
||||
__raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse)
|
||||
| AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
|
||||
| AT91_SMC_NRDPULSE_(config->nrd_pulse)
|
||||
| AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse),
|
||||
base + AT91_SMC_PULSE);
|
||||
|
||||
/* Cycle register */
|
||||
__raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle)
|
||||
| AT91_SMC_NRDCYCLE_(config->read_cycle),
|
||||
base + AT91_SMC_CYCLE);
|
||||
|
||||
/* Mode register */
|
||||
sam9_smc_cs_write_mode(base, config);
|
||||
}
|
||||
|
||||
void sam9_smc_configure(int id, int cs,
|
||||
struct sam9_smc_config *config)
|
||||
{
|
||||
sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(sam9_smc_configure);
|
||||
|
||||
static void sam9_smc_cs_read_mode(void __iomem *base,
|
||||
struct sam9_smc_config *config)
|
||||
{
|
||||
u32 val = __raw_readl(base + AT91_SMC_MODE);
|
||||
|
||||
config->mode = (val & ~AT91_SMC_NWECYCLE);
|
||||
config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ;
|
||||
}
|
||||
|
||||
void sam9_smc_read_mode(int id, int cs,
|
||||
struct sam9_smc_config *config)
|
||||
{
|
||||
sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(sam9_smc_read_mode);
|
||||
|
||||
static void sam9_smc_cs_read(void __iomem *base,
|
||||
struct sam9_smc_config *config)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* Setup register */
|
||||
val = __raw_readl(base + AT91_SMC_SETUP);
|
||||
|
||||
config->nwe_setup = val & AT91_SMC_NWESETUP;
|
||||
config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8;
|
||||
config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16;
|
||||
config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24;
|
||||
|
||||
/* Pulse register */
|
||||
val = __raw_readl(base + AT91_SMC_PULSE);
|
||||
|
||||
config->nwe_pulse = val & AT91_SMC_NWEPULSE;
|
||||
config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8;
|
||||
config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16;
|
||||
config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24;
|
||||
|
||||
/* Cycle register */
|
||||
val = __raw_readl(base + AT91_SMC_CYCLE);
|
||||
|
||||
config->write_cycle = val & AT91_SMC_NWECYCLE;
|
||||
config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16;
|
||||
|
||||
/* Mode register */
|
||||
sam9_smc_cs_read_mode(base, config);
|
||||
}
|
||||
|
||||
void sam9_smc_read(int id, int cs, struct sam9_smc_config *config)
|
||||
{
|
||||
sam9_smc_cs_read(AT91_SMC_CS(id, cs), config);
|
||||
}
|
||||
|
||||
void __init at91sam9_ioremap_smc(int id, u32 addr)
|
||||
{
|
||||
if (id > 1) {
|
||||
pr_warn("%s: id > 2\n", __func__);
|
||||
return;
|
||||
}
|
||||
smc_base_addr[id] = ioremap(addr, 512);
|
||||
if (!smc_base_addr[id])
|
||||
pr_warn("Impossible to ioremap smc.%d 0x%x\n", id, addr);
|
||||
}
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-at91/sam9_smc.
|
||||
*
|
||||
* Copyright (C) 2008 Andrew Victor
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
extern void __init at91sam9_ioremap_smc(int id, u32 addr);
|
||||
|
|
@ -835,7 +835,6 @@ config PATA_AT32
|
|||
config PATA_AT91
|
||||
tristate "PATA support for AT91SAM9260"
|
||||
depends on ARM && SOC_AT91SAM9
|
||||
depends on !ARCH_MULTIPLATFORM
|
||||
help
|
||||
This option enables support for IDE devices on the Atmel AT91SAM9260 SoC.
|
||||
|
||||
|
|
|
|||
|
|
@ -24,11 +24,13 @@
|
|||
#include <linux/ata.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/libata.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/mfd/syscon/atmel-smc.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/ata_platform.h>
|
||||
#include <linux/platform_data/atmel.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <mach/at91sam9_smc.h>
|
||||
#include <asm/gpio.h>
|
||||
|
||||
#define DRV_NAME "pata_at91"
|
||||
|
|
@ -57,6 +59,15 @@ struct smc_range {
|
|||
int max;
|
||||
};
|
||||
|
||||
struct regmap *smc;
|
||||
|
||||
struct at91sam9_smc_generic_fields {
|
||||
struct regmap_field *setup;
|
||||
struct regmap_field *pulse;
|
||||
struct regmap_field *cycle;
|
||||
struct regmap_field *mode;
|
||||
} fields;
|
||||
|
||||
/**
|
||||
* adjust_smc_value - adjust value for one of SMC registers.
|
||||
* @value: adjusted value
|
||||
|
|
@ -206,7 +217,6 @@ static void set_smc_timing(struct device *dev, struct ata_device *adev,
|
|||
{
|
||||
int ret = 0;
|
||||
int use_iordy;
|
||||
struct sam9_smc_config smc;
|
||||
unsigned int t6z; /* data tristate time in ns */
|
||||
unsigned int cycle; /* SMC Cycle width in MCK ticks */
|
||||
unsigned int setup; /* SMC Setup width in MCK ticks */
|
||||
|
|
@ -244,19 +254,21 @@ static void set_smc_timing(struct device *dev, struct ata_device *adev,
|
|||
|
||||
dev_dbg(dev, "Use IORDY=%u, TDF Cycles=%u\n", use_iordy, tdf_cycles);
|
||||
|
||||
/* SMC Setup Register */
|
||||
smc.nwe_setup = smc.nrd_setup = setup;
|
||||
smc.ncs_write_setup = smc.ncs_read_setup = 0;
|
||||
/* SMC Pulse Register */
|
||||
smc.nwe_pulse = smc.nrd_pulse = pulse;
|
||||
smc.ncs_write_pulse = smc.ncs_read_pulse = cs_pulse;
|
||||
/* SMC Cycle Register */
|
||||
smc.write_cycle = smc.read_cycle = cycle;
|
||||
/* SMC Mode Register*/
|
||||
smc.tdf_cycles = tdf_cycles;
|
||||
smc.mode = info->mode;
|
||||
|
||||
sam9_smc_configure(0, info->cs, &smc);
|
||||
regmap_fields_write(fields.setup, info->cs,
|
||||
AT91SAM9_SMC_NRDSETUP(setup) |
|
||||
AT91SAM9_SMC_NWESETUP(setup) |
|
||||
AT91SAM9_SMC_NCS_NRDSETUP(0) |
|
||||
AT91SAM9_SMC_NCS_WRSETUP(0));
|
||||
regmap_fields_write(fields.pulse, info->cs,
|
||||
AT91SAM9_SMC_NRDPULSE(pulse) |
|
||||
AT91SAM9_SMC_NWEPULSE(pulse) |
|
||||
AT91SAM9_SMC_NCS_NRDPULSE(cs_pulse) |
|
||||
AT91SAM9_SMC_NCS_WRPULSE(cs_pulse));
|
||||
regmap_fields_write(fields.cycle, info->cs,
|
||||
AT91SAM9_SMC_NRDCYCLE(cycle) |
|
||||
AT91SAM9_SMC_NWECYCLE(cycle));
|
||||
regmap_fields_write(fields.mode, info->cs, info->mode |
|
||||
AT91_SMC_TDF_(tdf_cycles));
|
||||
}
|
||||
|
||||
static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev)
|
||||
|
|
@ -280,21 +292,21 @@ static unsigned int pata_at91_data_xfer_noirq(struct ata_device *dev,
|
|||
{
|
||||
struct at91_ide_info *info = dev->link->ap->host->private_data;
|
||||
unsigned int consumed;
|
||||
unsigned int mode;
|
||||
unsigned long flags;
|
||||
struct sam9_smc_config smc;
|
||||
|
||||
local_irq_save(flags);
|
||||
sam9_smc_read_mode(0, info->cs, &smc);
|
||||
regmap_fields_read(fields.mode, info->cs, &mode);
|
||||
|
||||
/* set 16bit mode before writing data */
|
||||
smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_16;
|
||||
sam9_smc_write_mode(0, info->cs, &smc);
|
||||
regmap_fields_write(fields.mode, info->cs, (mode & ~AT91_SMC_DBW) |
|
||||
AT91_SMC_DBW_16);
|
||||
|
||||
consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
|
||||
|
||||
/* restore 8bit mode after data is written */
|
||||
smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_8;
|
||||
sam9_smc_write_mode(0, info->cs, &smc);
|
||||
regmap_fields_write(fields.mode, info->cs, (mode & ~AT91_SMC_DBW) |
|
||||
AT91_SMC_DBW_8);
|
||||
|
||||
local_irq_restore(flags);
|
||||
return consumed;
|
||||
|
|
@ -312,6 +324,36 @@ static struct ata_port_operations pata_at91_port_ops = {
|
|||
.cable_detect = ata_cable_40wire,
|
||||
};
|
||||
|
||||
static int at91sam9_smc_fields_init(struct device *dev)
|
||||
{
|
||||
struct reg_field field = REG_FIELD(0, 0, 31);
|
||||
|
||||
field.id_size = 8;
|
||||
field.id_offset = AT91SAM9_SMC_GENERIC_BLK_SZ;
|
||||
|
||||
field.reg = AT91SAM9_SMC_SETUP(AT91SAM9_SMC_GENERIC);
|
||||
fields.setup = devm_regmap_field_alloc(dev, smc, field);
|
||||
if (IS_ERR(fields.setup))
|
||||
return PTR_ERR(fields.setup);
|
||||
|
||||
field.reg = AT91SAM9_SMC_PULSE(AT91SAM9_SMC_GENERIC);
|
||||
fields.pulse = devm_regmap_field_alloc(dev, smc, field);
|
||||
if (IS_ERR(fields.pulse))
|
||||
return PTR_ERR(fields.pulse);
|
||||
|
||||
field.reg = AT91SAM9_SMC_CYCLE(AT91SAM9_SMC_GENERIC);
|
||||
fields.cycle = devm_regmap_field_alloc(dev, smc, field);
|
||||
if (IS_ERR(fields.cycle))
|
||||
return PTR_ERR(fields.cycle);
|
||||
|
||||
field.reg = AT91SAM9_SMC_MODE(AT91SAM9_SMC_GENERIC);
|
||||
fields.mode = devm_regmap_field_alloc(dev, smc, field);
|
||||
if (IS_ERR(fields.mode))
|
||||
return PTR_ERR(fields.mode);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pata_at91_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct at91_cf_data *board = dev_get_platdata(&pdev->dev);
|
||||
|
|
@ -341,6 +383,14 @@ static int pata_at91_probe(struct platform_device *pdev)
|
|||
|
||||
irq = board->irq_pin;
|
||||
|
||||
smc = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "atmel,smc");
|
||||
if (IS_ERR(smc))
|
||||
return PTR_ERR(smc);
|
||||
|
||||
ret = at91sam9_smc_fields_init(dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* init ata host */
|
||||
|
||||
host = ata_host_alloc(dev, 1);
|
||||
|
|
|
|||
|
|
@ -277,7 +277,6 @@ config AT91_CF
|
|||
tristate "AT91 CompactFlash Controller"
|
||||
depends on PCI
|
||||
depends on PCMCIA && ARCH_AT91
|
||||
depends on !ARCH_MULTIPLATFORM
|
||||
help
|
||||
Say Y here to support the CompactFlash controller on AT91 chips.
|
||||
Or choose M to compile the driver as a module named "at91_cf".
|
||||
|
|
|
|||
|
|
@ -20,16 +20,15 @@
|
|||
#include <linux/platform_data/atmel.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/mfd/syscon/atmel-mc.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_gpio.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <pcmcia/ss.h>
|
||||
|
||||
#include <mach/at91rm9200_mc.h>
|
||||
#include <mach/at91_ramc.h>
|
||||
|
||||
|
||||
/*
|
||||
* A0..A10 work in each range; A23 indicates I/O space; A25 is CFRNW;
|
||||
* some other bit in {A24,A22..A11} is nREG to flag memory access
|
||||
|
|
@ -40,6 +39,8 @@
|
|||
#define CF_IO_PHYS (1 << 23)
|
||||
#define CF_MEM_PHYS (0x017ff800)
|
||||
|
||||
struct regmap *mc;
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
|
||||
struct at91_cf_socket {
|
||||
|
|
@ -155,10 +156,7 @@ static int at91_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
|
|||
|
||||
/*
|
||||
* Use 16 bit accesses unless/until we need 8-bit i/o space.
|
||||
*/
|
||||
csr = at91_ramc_read(0, AT91_SMC_CSR(cf->board->chipselect)) & ~AT91_SMC_DBW;
|
||||
|
||||
/*
|
||||
*
|
||||
* NOTE: this CF controller ignores IOIS16, so we can't really do
|
||||
* MAP_AUTOSZ. The 16bit mode allows single byte access on either
|
||||
* D0-D7 (even addr) or D8-D15 (odd), so it's close enough for many
|
||||
|
|
@ -169,13 +167,14 @@ static int at91_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
|
|||
* CF 3.0 spec table 35 also giving the D8-D15 option.
|
||||
*/
|
||||
if (!(io->flags & (MAP_16BIT | MAP_AUTOSZ))) {
|
||||
csr |= AT91_SMC_DBW_8;
|
||||
csr = AT91_MC_SMC_DBW_8;
|
||||
dev_dbg(&cf->pdev->dev, "8bit i/o bus\n");
|
||||
} else {
|
||||
csr |= AT91_SMC_DBW_16;
|
||||
csr = AT91_MC_SMC_DBW_16;
|
||||
dev_dbg(&cf->pdev->dev, "16bit i/o bus\n");
|
||||
}
|
||||
at91_ramc_write(0, AT91_SMC_CSR(cf->board->chipselect), csr);
|
||||
regmap_update_bits(mc, AT91_MC_SMC_CSR(cf->board->chipselect),
|
||||
AT91_MC_SMC_DBW, csr);
|
||||
|
||||
io->start = cf->socket.io_offset;
|
||||
io->stop = io->start + SZ_2K - 1;
|
||||
|
|
@ -236,6 +235,10 @@ static int at91_cf_dt_init(struct platform_device *pdev)
|
|||
|
||||
pdev->dev.platform_data = board;
|
||||
|
||||
mc = syscon_regmap_lookup_by_compatible("atmel,at91rm9200-sdramc");
|
||||
if (IS_ERR(mc))
|
||||
return PTR_ERR(mc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -0,0 +1,144 @@
|
|||
/*
|
||||
* Copyright (C) 2005 Ivan Kokshaysky
|
||||
* Copyright (C) SAN People
|
||||
*
|
||||
* Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals
|
||||
* registers.
|
||||
* Based on AT91RM9200 datasheet revision E.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_MFD_SYSCON_ATMEL_MC_H_
|
||||
#define _LINUX_MFD_SYSCON_ATMEL_MC_H_
|
||||
|
||||
/* Memory Controller */
|
||||
#define AT91_MC_RCR 0x00
|
||||
#define AT91_MC_RCB BIT(0)
|
||||
|
||||
#define AT91_MC_ASR 0x04
|
||||
#define AT91_MC_UNADD BIT(0)
|
||||
#define AT91_MC_MISADD BIT(1)
|
||||
#define AT91_MC_ABTSZ GENMASK(9, 8)
|
||||
#define AT91_MC_ABTSZ_BYTE (0 << 8)
|
||||
#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
|
||||
#define AT91_MC_ABTSZ_WORD (2 << 8)
|
||||
#define AT91_MC_ABTTYP GENMASK(11, 10)
|
||||
#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
|
||||
#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
|
||||
#define AT91_MC_ABTTYP_FETCH (2 << 10)
|
||||
#define AT91_MC_MST(n) BIT(16 + (n))
|
||||
#define AT91_MC_SVMST(n) BIT(24 + (n))
|
||||
|
||||
#define AT91_MC_AASR 0x08
|
||||
|
||||
#define AT91_MC_MPR 0x0c
|
||||
#define AT91_MPR_MSTP(n) GENMASK(2 + ((x) * 4), ((x) * 4))
|
||||
|
||||
/* External Bus Interface (EBI) registers */
|
||||
#define AT91_MC_EBI_CSA 0x60
|
||||
#define AT91_MC_EBI_CS(n) BIT(x)
|
||||
#define AT91_MC_EBI_NUM_CS 8
|
||||
|
||||
#define AT91_MC_EBI_CFGR 0x64
|
||||
#define AT91_MC_EBI_DBPUC BIT(0)
|
||||
|
||||
/* Static Memory Controller (SMC) registers */
|
||||
#define AT91_MC_SMC_CSR(n) (0x70 + ((n) * 4))
|
||||
#define AT91_MC_SMC_NWS GENMASK(6, 0)
|
||||
#define AT91_MC_SMC_NWS_(x) ((x) << 0)
|
||||
#define AT91_MC_SMC_WSEN BIT(7)
|
||||
#define AT91_MC_SMC_TDF GENMASK(11, 8)
|
||||
#define AT91_MC_SMC_TDF_(x) ((x) << 8)
|
||||
#define AT91_MC_SMC_TDF_MAX 0xf
|
||||
#define AT91_MC_SMC_BAT BIT(12)
|
||||
#define AT91_MC_SMC_DBW GENMASK(14, 13)
|
||||
#define AT91_MC_SMC_DBW_16 (1 << 13)
|
||||
#define AT91_MC_SMC_DBW_8 (2 << 13)
|
||||
#define AT91_MC_SMC_DPR BIT(15)
|
||||
#define AT91_MC_SMC_ACSS GENMASK(17, 16)
|
||||
#define AT91_MC_SMC_ACSS_(x) ((x) << 16)
|
||||
#define AT91_MC_SMC_ACSS_MAX 3
|
||||
#define AT91_MC_SMC_RWSETUP GENMASK(26, 24)
|
||||
#define AT91_MC_SMC_RWSETUP_(x) ((x) << 24)
|
||||
#define AT91_MC_SMC_RWHOLD GENMASK(30, 28)
|
||||
#define AT91_MC_SMC_RWHOLD_(x) ((x) << 28)
|
||||
#define AT91_MC_SMC_RWHOLDSETUP_MAX 7
|
||||
|
||||
/* SDRAM Controller registers */
|
||||
#define AT91_MC_SDRAMC_MR 0x90
|
||||
#define AT91_MC_SDRAMC_MODE GENMASK(3, 0)
|
||||
#define AT91_MC_SDRAMC_MODE_NORMAL (0 << 0)
|
||||
#define AT91_MC_SDRAMC_MODE_NOP (1 << 0)
|
||||
#define AT91_MC_SDRAMC_MODE_PRECHARGE (2 << 0)
|
||||
#define AT91_MC_SDRAMC_MODE_LMR (3 << 0)
|
||||
#define AT91_MC_SDRAMC_MODE_REFRESH (4 << 0)
|
||||
#define AT91_MC_SDRAMC_DBW_16 BIT(4)
|
||||
|
||||
#define AT91_MC_SDRAMC_TR 0x94
|
||||
#define AT91_MC_SDRAMC_COUNT GENMASK(11, 0)
|
||||
|
||||
#define AT91_MC_SDRAMC_CR 0x98
|
||||
#define AT91_MC_SDRAMC_NC GENMASK(1, 0)
|
||||
#define AT91_MC_SDRAMC_NC_8 (0 << 0)
|
||||
#define AT91_MC_SDRAMC_NC_9 (1 << 0)
|
||||
#define AT91_MC_SDRAMC_NC_10 (2 << 0)
|
||||
#define AT91_MC_SDRAMC_NC_11 (3 << 0)
|
||||
#define AT91_MC_SDRAMC_NR GENMASK(3, 2)
|
||||
#define AT91_MC_SDRAMC_NR_11 (0 << 2)
|
||||
#define AT91_MC_SDRAMC_NR_12 (1 << 2)
|
||||
#define AT91_MC_SDRAMC_NR_13 (2 << 2)
|
||||
#define AT91_MC_SDRAMC_NB BIT(4)
|
||||
#define AT91_MC_SDRAMC_NB_2 (0 << 4)
|
||||
#define AT91_MC_SDRAMC_NB_4 (1 << 4)
|
||||
#define AT91_MC_SDRAMC_CAS GENMASK(6, 5)
|
||||
#define AT91_MC_SDRAMC_CAS_2 (2 << 5)
|
||||
#define AT91_MC_SDRAMC_TWR GENMASK(10, 7)
|
||||
#define AT91_MC_SDRAMC_TRC GENMASK(14, 11)
|
||||
#define AT91_MC_SDRAMC_TRP GENMASK(18, 15)
|
||||
#define AT91_MC_SDRAMC_TRCD GENMASK(22, 19)
|
||||
#define AT91_MC_SDRAMC_TRAS GENMASK(26, 23)
|
||||
#define AT91_MC_SDRAMC_TXSR GENMASK(30, 27)
|
||||
|
||||
#define AT91_MC_SDRAMC_SRR 0x9c
|
||||
#define AT91_MC_SDRAMC_SRCB BIT(0)
|
||||
|
||||
#define AT91_MC_SDRAMC_LPR 0xa0
|
||||
#define AT91_MC_SDRAMC_LPCB BIT(0)
|
||||
|
||||
#define AT91_MC_SDRAMC_IER 0xa4
|
||||
#define AT91_MC_SDRAMC_IDR 0xa8
|
||||
#define AT91_MC_SDRAMC_IMR 0xac
|
||||
#define AT91_MC_SDRAMC_ISR 0xb0
|
||||
#define AT91_MC_SDRAMC_RES BIT(0)
|
||||
|
||||
/* Burst Flash Controller register */
|
||||
#define AT91_MC_BFC_MR 0xc0
|
||||
#define AT91_MC_BFC_BFCOM GENMASK(1, 0)
|
||||
#define AT91_MC_BFC_BFCOM_DISABLED (0 << 0)
|
||||
#define AT91_MC_BFC_BFCOM_ASYNC (1 << 0)
|
||||
#define AT91_MC_BFC_BFCOM_BURST (2 << 0)
|
||||
#define AT91_MC_BFC_BFCC GENMASK(3, 2)
|
||||
#define AT91_MC_BFC_BFCC_MCK (1 << 2)
|
||||
#define AT91_MC_BFC_BFCC_DIV2 (2 << 2)
|
||||
#define AT91_MC_BFC_BFCC_DIV4 (3 << 2)
|
||||
#define AT91_MC_BFC_AVL GENMASK(7, 4)
|
||||
#define AT91_MC_BFC_PAGES GENMASK(10, 8)
|
||||
#define AT91_MC_BFC_PAGES_NO_PAGE (0 << 8)
|
||||
#define AT91_MC_BFC_PAGES_16 (1 << 8)
|
||||
#define AT91_MC_BFC_PAGES_32 (2 << 8)
|
||||
#define AT91_MC_BFC_PAGES_64 (3 << 8)
|
||||
#define AT91_MC_BFC_PAGES_128 (4 << 8)
|
||||
#define AT91_MC_BFC_PAGES_256 (5 << 8)
|
||||
#define AT91_MC_BFC_PAGES_512 (6 << 8)
|
||||
#define AT91_MC_BFC_PAGES_1024 (7 << 8)
|
||||
#define AT91_MC_BFC_OEL GENMASK(13, 12)
|
||||
#define AT91_MC_BFC_BAAEN BIT(16)
|
||||
#define AT91_MC_BFC_BFOEH BIT(17)
|
||||
#define AT91_MC_BFC_MUXEN BIT(18)
|
||||
#define AT91_MC_BFC_RDYEN BIT(19)
|
||||
|
||||
#endif /* _LINUX_MFD_SYSCON_ATMEL_MC_H_ */
|
||||
|
|
@ -1,63 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
|
||||
*
|
||||
* Copyright (C) 2005 Ivan Kokshaysky
|
||||
* Copyright (C) SAN People
|
||||
*
|
||||
* Memory Controllers (SDRAMC only) - System peripherals registers.
|
||||
* Based on AT91RM9200 datasheet revision E.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91RM9200_SDRAMC_H
|
||||
#define AT91RM9200_SDRAMC_H
|
||||
|
||||
/* SDRAM Controller registers */
|
||||
#define AT91RM9200_SDRAMC_MR 0x90 /* Mode Register */
|
||||
#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */
|
||||
#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0)
|
||||
#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0)
|
||||
#define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0)
|
||||
#define AT91RM9200_SDRAMC_MODE_LMR (3 << 0)
|
||||
#define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0)
|
||||
#define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */
|
||||
#define AT91RM9200_SDRAMC_DBW_32 (0 << 4)
|
||||
#define AT91RM9200_SDRAMC_DBW_16 (1 << 4)
|
||||
|
||||
#define AT91RM9200_SDRAMC_TR 0x94 /* Refresh Timer Register */
|
||||
#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
|
||||
|
||||
#define AT91RM9200_SDRAMC_CR 0x98 /* Configuration Register */
|
||||
#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */
|
||||
#define AT91RM9200_SDRAMC_NC_8 (0 << 0)
|
||||
#define AT91RM9200_SDRAMC_NC_9 (1 << 0)
|
||||
#define AT91RM9200_SDRAMC_NC_10 (2 << 0)
|
||||
#define AT91RM9200_SDRAMC_NC_11 (3 << 0)
|
||||
#define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */
|
||||
#define AT91RM9200_SDRAMC_NR_11 (0 << 2)
|
||||
#define AT91RM9200_SDRAMC_NR_12 (1 << 2)
|
||||
#define AT91RM9200_SDRAMC_NR_13 (2 << 2)
|
||||
#define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */
|
||||
#define AT91RM9200_SDRAMC_NB_2 (0 << 4)
|
||||
#define AT91RM9200_SDRAMC_NB_4 (1 << 4)
|
||||
#define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */
|
||||
#define AT91RM9200_SDRAMC_CAS_2 (2 << 5)
|
||||
#define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
|
||||
#define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
|
||||
#define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
|
||||
#define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
|
||||
#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
|
||||
#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
|
||||
|
||||
#define AT91RM9200_SDRAMC_SRR 0x9c /* Self Refresh Register */
|
||||
#define AT91RM9200_SDRAMC_LPR 0xa0 /* Low Power Register */
|
||||
#define AT91RM9200_SDRAMC_IER 0xa4 /* Interrupt Enable Register */
|
||||
#define AT91RM9200_SDRAMC_IDR 0xa8 /* Interrupt Disable Register */
|
||||
#define AT91RM9200_SDRAMC_IMR 0xac /* Interrupt Mask Register */
|
||||
#define AT91RM9200_SDRAMC_ISR 0xb0 /* Interrupt Status Register */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue