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drm/amdgpu/powerplay/smu7: drop refresh rate checks for mclk switching 

The logic has moved to cgs.  mclk switching with DC at higher refresh
rates should work.

Reviewed-by: Eric Huang <JinhuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
This commit is contained in:
Alex Deucher 2018-02-13 14:37:36 -05:00
parent 7a572b1eda
commit d821792171
1 changed files with 1 additions and 2 deletions
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3
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
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@ -2909,8 +2909,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
else
disable_mclk_switching = ((1 < info.display_count) ||
disable_mclk_switching_for_frame_lock ||
smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) ||
(mode_info.refresh_rate > 120));
smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us));
sclk = smu7_ps->performance_levels[0].engine_clock;
mclk = smu7_ps->performance_levels[0].memory_clock;