mirror of https://gitee.com/openkylin/linux.git
drm/i915/icl: Default to Thread Group preemption for compute workloads
We assumed that the default preemption granularity is fine for ICL. Unfortunately, it turns out that some drivers don't support mid-thread preemption for compute workloads. If a workload that doesn't support mid-thread preemption gets mid-thread preempted, we're going to observe a GPU hang. While I'm here, let's also update the "workaround" naming. Signed-off-by: Michał Winiarski <michal.winiarski@intel.com> Cc: Anuj Phogat <anuj.phogat@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Rafael Antognolli <rafael.antognolli@intel.com> Tested-by: Anuj Phogat <anuj.phogat@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rafael Antognolli <rafael.antognolli@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190305124827.23446-1-michal.winiarski@intel.com
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@ -555,6 +555,11 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine)
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GEN10_CACHE_MODE_SS,
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0, /* write-only, so skip validation */
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_MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
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/* WaDisableGPGPUMidThreadPreemption:icl */
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WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
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GEN9_PREEMPT_GPGPU_LEVEL_MASK,
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GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
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}
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void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
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@ -1162,8 +1167,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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GEN7_DISABLE_SAMPLER_PREFETCH);
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}
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if (IS_GEN(i915, 9) || IS_CANNONLAKE(i915)) {
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/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */
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if (IS_GEN_RANGE(i915, 9, 11)) {
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/* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl */
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wa_masked_en(wal,
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GEN7_FF_SLICE_CS_CHICKEN1,
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GEN9_FFSC_PERCTX_PREEMPT_CTRL);
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