mirror of https://gitee.com/openkylin/linux.git
ARM: meson: Add SMP bringup code for Meson8 and Meson8b
This adds the necessary SMP-operations and startup code to use the additional cores on the Amlogic Meson8/Meson8m2 (both are using the same sequence) and Meson8b (using a slightly difference sequence) SoCs. Signed-off-by: Carlo Caione <carlo@endlessm.com> [add Meson8/Meson8m2 support and allow taking CPU cores offline as well] Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This commit is contained in:
Martin Blumenstingl
Kevin Hilman
parent
936a417443
commit
d850f3e5d2
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@ -147,6 +147,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000
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endif
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textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
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textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
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textofs-$(CONFIG_ARCH_MESON) := 0x00208000
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textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
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# Machine directory name. This list is sorted alphanumerically
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@ -9,6 +9,7 @@ menuconfig ARCH_MESON
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select PINCTRL_MESON
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select COMMON_CLK
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select COMMON_CLK_AMLOGIC
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select HAVE_ARM_SCU if SMP
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if ARCH_MESON
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@ -1 +1,2 @@
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obj-$(CONFIG_ARCH_MESON) += meson.o
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obj-$(CONFIG_SMP) += platsmp.o
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@ -0,0 +1,440 @@
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/*
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* Copyright (C) 2015 Carlo Caione <carlo@endlessm.com>
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* Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/smp.h>
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#include <linux/mfd/syscon.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/smp_scu.h>
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#include <asm/smp_plat.h>
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#define MESON_SMP_SRAM_CPU_CTRL_REG (0x00)
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#define MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(c) (0x04 + ((c - 1) << 2))
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#define MESON_CPU_AO_RTI_PWR_A9_CNTL0 (0x00)
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#define MESON_CPU_AO_RTI_PWR_A9_CNTL1 (0x04)
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#define MESON_CPU_AO_RTI_PWR_A9_MEM_PD0 (0x14)
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#define MESON_CPU_PWR_A9_CNTL0_M(c) (0x03 << ((c * 2) + 16))
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#define MESON_CPU_PWR_A9_CNTL1_M(c) (0x03 << ((c + 1) << 1))
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#define MESON_CPU_PWR_A9_MEM_PD0_M(c) (0x0f << (32 - (c * 4)))
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#define MESON_CPU_PWR_A9_CNTL1_ST(c) (0x01 << (c + 16))
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static void __iomem *sram_base;
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static void __iomem *scu_base;
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static struct regmap *pmu;
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static struct reset_control *meson_smp_get_core_reset(int cpu)
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{
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struct device_node *np = of_get_cpu_node(cpu, 0);
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return of_reset_control_get_exclusive(np, NULL);
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}
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static void meson_smp_set_cpu_ctrl(int cpu, bool on_off)
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{
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u32 val = readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_REG);
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if (on_off)
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val |= BIT(cpu);
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else
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val &= ~BIT(cpu);
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/* keep bit 0 always enabled */
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val |= BIT(0);
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writel(val, sram_base + MESON_SMP_SRAM_CPU_CTRL_REG);
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}
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static void __init meson_smp_prepare_cpus(const char *scu_compatible,
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const char *pmu_compatible,
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const char *sram_compatible)
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{
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static struct device_node *node;
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/* SMP SRAM */
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node = of_find_compatible_node(NULL, NULL, sram_compatible);
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if (!node) {
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pr_err("Missing SRAM node\n");
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return;
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}
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sram_base = of_iomap(node, 0);
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if (!sram_base) {
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pr_err("Couldn't map SRAM registers\n");
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return;
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}
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/* PMU */
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pmu = syscon_regmap_lookup_by_compatible(pmu_compatible);
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if (IS_ERR(pmu)) {
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pr_err("Couldn't map PMU registers\n");
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return;
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}
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/* SCU */
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node = of_find_compatible_node(NULL, NULL, scu_compatible);
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if (!node) {
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pr_err("Missing SCU node\n");
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return;
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}
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scu_base = of_iomap(node, 0);
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if (!scu_base) {
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pr_err("Couln't map SCU registers\n");
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return;
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}
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scu_enable(scu_base);
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}
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static void __init meson8b_smp_prepare_cpus(unsigned int max_cpus)
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{
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meson_smp_prepare_cpus("arm,cortex-a5-scu", "amlogic,meson8b-pmu",
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"amlogic,meson8b-smp-sram");
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}
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static void __init meson8_smp_prepare_cpus(unsigned int max_cpus)
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{
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meson_smp_prepare_cpus("arm,cortex-a9-scu", "amlogic,meson8-pmu",
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"amlogic,meson8-smp-sram");
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}
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static void meson_smp_begin_secondary_boot(unsigned int cpu)
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{
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/*
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* Set the entry point before powering on the CPU through the SCU. This
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* is needed if the CPU is in "warm" state (= after rebooting the
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* system without power-cycling, or when taking the CPU offline and
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* then taking it online again.
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*/
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writel(__pa_symbol(secondary_startup),
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sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu));
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/*
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* SCU Power on CPU (needs to be done before starting the CPU,
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* otherwise the secondary CPU will not start).
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*/
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scu_cpu_power_enable(scu_base, cpu);
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}
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static int meson_smp_finalize_secondary_boot(unsigned int cpu)
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{
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unsigned long timeout;
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timeout = jiffies + (10 * HZ);
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while (readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu))) {
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if (!time_before(jiffies, timeout)) {
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pr_err("Timeout while waiting for CPU%d status\n",
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cpu);
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return -ETIMEDOUT;
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}
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}
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writel(__pa_symbol(secondary_startup),
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sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu));
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meson_smp_set_cpu_ctrl(cpu, true);
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return 0;
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}
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static int meson8_smp_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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{
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struct reset_control *rstc;
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int ret;
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rstc = meson_smp_get_core_reset(cpu);
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if (IS_ERR(rstc)) {
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pr_err("Couldn't get the reset controller for CPU%d\n", cpu);
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return PTR_ERR(rstc);
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}
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meson_smp_begin_secondary_boot(cpu);
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/* Reset enable */
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ret = reset_control_assert(rstc);
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if (ret) {
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pr_err("Failed to assert CPU%d reset\n", cpu);
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goto out;
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}
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/* CPU power ON */
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ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
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MESON_CPU_PWR_A9_CNTL1_M(cpu), 0);
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if (ret < 0) {
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pr_err("Couldn't wake up CPU%d\n", cpu);
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goto out;
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}
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udelay(10);
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/* Isolation disable */
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ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
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0);
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if (ret < 0) {
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pr_err("Error when disabling isolation of CPU%d\n", cpu);
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goto out;
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}
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/* Reset disable */
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ret = reset_control_deassert(rstc);
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if (ret) {
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pr_err("Failed to de-assert CPU%d reset\n", cpu);
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goto out;
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}
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ret = meson_smp_finalize_secondary_boot(cpu);
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if (ret)
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goto out;
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out:
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reset_control_put(rstc);
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return 0;
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}
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static int meson8b_smp_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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{
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struct reset_control *rstc;
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int ret;
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u32 val;
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rstc = meson_smp_get_core_reset(cpu);
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if (IS_ERR(rstc)) {
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pr_err("Couldn't get the reset controller for CPU%d\n", cpu);
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return PTR_ERR(rstc);
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}
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meson_smp_begin_secondary_boot(cpu);
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/* CPU power UP */
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ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
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MESON_CPU_PWR_A9_CNTL0_M(cpu), 0);
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if (ret < 0) {
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pr_err("Couldn't power up CPU%d\n", cpu);
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goto out;
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}
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udelay(5);
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/* Reset enable */
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ret = reset_control_assert(rstc);
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if (ret) {
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pr_err("Failed to assert CPU%d reset\n", cpu);
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goto out;
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}
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/* Memory power UP */
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ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0,
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MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0);
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if (ret < 0) {
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pr_err("Couldn't power up the memory for CPU%d\n", cpu);
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goto out;
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}
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/* Wake up CPU */
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ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
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MESON_CPU_PWR_A9_CNTL1_M(cpu), 0);
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if (ret < 0) {
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pr_err("Couldn't wake up CPU%d\n", cpu);
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goto out;
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}
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udelay(10);
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ret = regmap_read_poll_timeout(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, val,
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val & MESON_CPU_PWR_A9_CNTL1_ST(cpu),
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10, 10000);
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if (ret) {
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pr_err("Timeout while polling PMU for CPU%d status\n", cpu);
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goto out;
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}
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/* Isolation disable */
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ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
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0);
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if (ret < 0) {
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pr_err("Error when disabling isolation of CPU%d\n", cpu);
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goto out;
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}
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/* Reset disable */
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ret = reset_control_deassert(rstc);
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if (ret) {
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pr_err("Failed to de-assert CPU%d reset\n", cpu);
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goto out;
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}
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ret = meson_smp_finalize_secondary_boot(cpu);
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if (ret)
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goto out;
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out:
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reset_control_put(rstc);
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return 0;
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static void meson8_smp_cpu_die(unsigned int cpu)
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{
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meson_smp_set_cpu_ctrl(cpu, false);
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v7_exit_coherency_flush(louis);
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scu_power_mode(scu_base, SCU_PM_POWEROFF);
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dsb();
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wfi();
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/* we should never get here */
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WARN_ON(1);
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}
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static int meson8_smp_cpu_kill(unsigned int cpu)
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{
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int ret, power_mode;
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unsigned long timeout;
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timeout = jiffies + (50 * HZ);
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do {
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power_mode = scu_get_cpu_power_mode(scu_base, cpu);
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if (power_mode == SCU_PM_POWEROFF)
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break;
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usleep_range(10000, 15000);
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} while (time_before(jiffies, timeout));
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if (power_mode != SCU_PM_POWEROFF) {
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pr_err("Error while waiting for SCU power-off on CPU%d\n",
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cpu);
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return -ETIMEDOUT;
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}
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msleep(30);
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/* Isolation enable */
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ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
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0x3);
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if (ret < 0) {
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pr_err("Error when enabling isolation for CPU%d\n", cpu);
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return ret;
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}
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udelay(10);
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/* CPU power OFF */
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ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
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MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3);
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if (ret < 0) {
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pr_err("Couldn't change sleep status of CPU%d\n", cpu);
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return ret;
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}
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return 1;
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}
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static int meson8b_smp_cpu_kill(unsigned int cpu)
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{
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int ret, power_mode, count = 5000;
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do {
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power_mode = scu_get_cpu_power_mode(scu_base, cpu);
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if (power_mode == SCU_PM_POWEROFF)
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break;
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udelay(10);
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} while (++count);
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if (power_mode != SCU_PM_POWEROFF) {
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pr_err("Error while waiting for SCU power-off on CPU%d\n",
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cpu);
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return -ETIMEDOUT;
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}
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udelay(10);
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/* CPU power DOWN */
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ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
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MESON_CPU_PWR_A9_CNTL0_M(cpu), 0x3);
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if (ret < 0) {
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pr_err("Couldn't power down CPU%d\n", cpu);
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return ret;
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}
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/* Isolation enable */
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ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
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0x3);
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if (ret < 0) {
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pr_err("Error when enabling isolation for CPU%d\n", cpu);
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return ret;
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}
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udelay(10);
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/* Sleep status */
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ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
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MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3);
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if (ret < 0) {
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pr_err("Couldn't change sleep status of CPU%d\n", cpu);
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return ret;
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}
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/* Memory power DOWN */
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ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0,
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MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0xf);
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if (ret < 0) {
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pr_err("Couldn't power down the memory of CPU%d\n", cpu);
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return ret;
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}
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return 1;
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}
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#endif
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static struct smp_operations meson8_smp_ops __initdata = {
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.smp_prepare_cpus = meson8_smp_prepare_cpus,
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.smp_boot_secondary = meson8_smp_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = meson8_smp_cpu_die,
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.cpu_kill = meson8_smp_cpu_kill,
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#endif
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};
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static struct smp_operations meson8b_smp_ops __initdata = {
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.smp_prepare_cpus = meson8b_smp_prepare_cpus,
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.smp_boot_secondary = meson8b_smp_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = meson8_smp_cpu_die,
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.cpu_kill = meson8b_smp_cpu_kill,
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#endif
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};
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CPU_METHOD_OF_DECLARE(meson8_smp, "amlogic,meson8-smp", &meson8_smp_ops);
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CPU_METHOD_OF_DECLARE(meson8b_smp, "amlogic,meson8b-smp", &meson8b_smp_ops);
|
||||
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Reference in New Issue