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drm/i915: don't set the FBC plane select bits on HSW+ 

This commit is just to make the intentions explicit: on HSW+ these
bits are MBZ, but since we only support plane A and the macro
evaluates to zero when plane A is the parameter, we're not fixing any
bug.

v2:
 - Remove useless extra blank like (Chris).
 - Init dpfc_ctl in another place (Chris).

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Paulo Zanoni 2015-06-12 14:36:21 -03:00 committed by Daniel Vetter
parent 2e8144a53d
commit d8514d6306
1 changed files with 4 additions and 1 deletions
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5
drivers/gpu/drm/i915/intel_fbc.c
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@ -262,7 +262,10 @@ static void gen7_fbc_enable(struct drm_crtc *crtc)
dev_priv->fbc.enabled = true;
dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
dpfc_ctl = 0;
if (IS_IVYBRIDGE(dev))
dpfc_ctl |= IVB_DPFC_CTL_PLANE(intel_crtc->plane);
if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
dev_priv->fbc.threshold++;