openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

mtd: nand: qcom: fix read failure without complete bootchain 

The NAND page read fails without complete boot chain since
NAND_DEV_CMD_VLD value is not proper. The default power on reset
value for this register is

    0xe - ERASE_START_VALID | WRITE_START_VALID | READ_STOP_VALID

The READ_START_VALID should be enabled for sending PAGE_READ
command. READ_STOP_VALID should be cleared since normal NAND
page read does not require READ_STOP command.

Fixes: c76b78d8ec ("mtd: nand: Qualcomm NAND controller driver")
Cc: stable@vger.kernel.org
Reviewed-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This commit is contained in:
Abhishek Sahu 2017-08-11 17:09:16 +05:30 committed by Boris Brezillon
parent 238709b220
commit d8a9b320a2
1 changed files with 12 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/mtd/nand/qcom_nandc.c
View File

@ -109,7 +109,11 @@
#define READ_ADDR 0 #define READ_ADDR 0
/* NAND_DEV_CMD_VLD bits */ /* NAND_DEV_CMD_VLD bits */
#define READ_START_VLD 0 #define READ_START_VLD BIT(0)
#define READ_STOP_VLD BIT(1)
#define WRITE_START_VLD BIT(2)
#define ERASE_START_VLD BIT(3)
#define SEQ_READ_START_VLD BIT(4)
/* NAND_EBI2_ECC_BUF_CFG bits */ /* NAND_EBI2_ECC_BUF_CFG bits */
#define NUM_STEPS 0 #define NUM_STEPS 0
@ -148,6 +152,10 @@
#define FETCH_ID 0xb #define FETCH_ID 0xb
#define RESET_DEVICE 0xd #define RESET_DEVICE 0xd
/* Default Value for NAND_DEV_CMD_VLD */
#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \
ERASE_START_VLD | SEQ_READ_START_VLD)
/* /*
* the NAND controller performs reads/writes with ECC in 516 byte chunks. * the NAND controller performs reads/writes with ECC in 516 byte chunks.
* the driver calls the chunks 'step' or 'codeword' interchangeably * the driver calls the chunks 'step' or 'codeword' interchangeably
@ -695,8 +703,7 @@ static int nandc_param(struct qcom_nand_host *host)
/* configure CMD1 and VLD for ONFI param probing */ /* configure CMD1 and VLD for ONFI param probing */
nandc_set_reg(nandc, NAND_DEV_CMD_VLD, nandc_set_reg(nandc, NAND_DEV_CMD_VLD,
(nandc->vld & ~(1 << READ_START_VLD)) (nandc->vld & ~READ_START_VLD));
| 0 << READ_START_VLD);
nandc_set_reg(nandc, NAND_DEV_CMD1, nandc_set_reg(nandc, NAND_DEV_CMD1,
(nandc->cmd1 & ~(0xFF << READ_ADDR)) (nandc->cmd1 & ~(0xFF << READ_ADDR))
| NAND_CMD_PARAM << READ_ADDR); | NAND_CMD_PARAM << READ_ADDR);
@ -1995,13 +2002,14 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
{ {
/* kill onenand */ /* kill onenand */
nandc_write(nandc, SFLASHC_BURST_CFG, 0); nandc_write(nandc, SFLASHC_BURST_CFG, 0);
nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
/* enable ADM DMA */ /* enable ADM DMA */
nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN); nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
/* save the original values of these registers */ /* save the original values of these registers */
nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1); nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);
nandc->vld = nandc_read(nandc, NAND_DEV_CMD_VLD); nandc->vld = NAND_DEV_CMD_VLD_VAL;
return 0; return 0;
} }