mirror of https://gitee.com/openkylin/linux.git
ARM: S5PV310: Add support External Interrupt
This patch adds EINT(External Interrupt) support on S5PV310 and S5PC210. All EINTs are transferred to GIC through interrupt combiner. Signed-off-by: Jongsun Han <jongsun.han@samsung.com> Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Jongsun Han
Kukjin Kim
parent
40c9bc5c3c
commit
d8bb31e68f
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@ -13,7 +13,7 @@ obj- :=
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# Core support for S5PV310 system
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obj-$(CONFIG_CPU_S5PV310) += cpu.o init.o clock.o irq-combiner.o
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obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o gpiolib.o
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obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o gpiolib.o irq-eint.o
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
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@ -0,0 +1,228 @@
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/* linux/arch/arm/mach-s5pv310/irq-eint.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* S5PV310 - IRQ EINT support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/sysdev.h>
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#include <linux/gpio.h>
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#include <plat/pm.h>
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#include <plat/cpu.h>
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#include <plat/gpio-cfg.h>
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#include <mach/regs-gpio.h>
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static DEFINE_SPINLOCK(eint_lock);
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static unsigned int eint0_15_data[16];
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static unsigned int s5pv310_get_irq_nr(unsigned int number)
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{
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u32 ret = 0;
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switch (number) {
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case 0 ... 3:
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ret = (number + IRQ_EINT0);
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break;
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case 4 ... 7:
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ret = (number + (IRQ_EINT4 - 4));
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break;
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case 8 ... 15:
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ret = (number + (IRQ_EINT8 - 8));
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break;
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default:
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printk(KERN_ERR "number available : %d\n", number);
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}
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return ret;
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}
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static inline void s5pv310_irq_eint_mask(unsigned int irq)
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{
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u32 mask;
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spin_lock(&eint_lock);
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mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
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mask |= eint_irq_to_bit(irq);
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__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
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spin_unlock(&eint_lock);
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}
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static void s5pv310_irq_eint_unmask(unsigned int irq)
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{
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u32 mask;
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spin_lock(&eint_lock);
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mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
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mask &= ~(eint_irq_to_bit(irq));
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__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
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spin_unlock(&eint_lock);
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}
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static inline void s5pv310_irq_eint_ack(unsigned int irq)
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{
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__raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
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}
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static void s5pv310_irq_eint_maskack(unsigned int irq)
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{
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s5pv310_irq_eint_mask(irq);
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s5pv310_irq_eint_ack(irq);
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}
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static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type)
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{
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int offs = EINT_OFFSET(irq);
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int shift;
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u32 ctrl, mask;
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u32 newvalue = 0;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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newvalue = S5P_IRQ_TYPE_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
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break;
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default:
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printk(KERN_ERR "No such irq type %d", type);
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return -EINVAL;
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}
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shift = (offs & 0x7) * 4;
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mask = 0x7 << shift;
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spin_lock(&eint_lock);
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ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq)));
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ctrl &= ~mask;
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ctrl |= newvalue << shift;
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__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq)));
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spin_unlock(&eint_lock);
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switch (offs) {
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case 0 ... 7:
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s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
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break;
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case 8 ... 15:
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s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
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break;
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case 16 ... 23:
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s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
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break;
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case 24 ... 31:
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s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
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break;
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default:
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printk(KERN_ERR "No such irq number %d", offs);
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}
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return 0;
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}
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static struct irq_chip s5pv310_irq_eint = {
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.name = "s5pv310-eint",
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.mask = s5pv310_irq_eint_mask,
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.unmask = s5pv310_irq_eint_unmask,
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.mask_ack = s5pv310_irq_eint_maskack,
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.ack = s5pv310_irq_eint_ack,
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.set_type = s5pv310_irq_eint_set_type,
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#ifdef CONFIG_PM
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.set_wake = s3c_irqext_wake,
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#endif
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};
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/* s5pv310_irq_demux_eint
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*
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* This function demuxes the IRQ from from EINTs 16 to 31.
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* It is designed to be inlined into the specific handler
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* s5p_irq_demux_eintX_Y.
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*
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* Each EINT pend/mask registers handle eight of them.
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*/
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static inline void s5pv310_irq_demux_eint(unsigned int start)
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{
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unsigned int irq;
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u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
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u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
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status &= ~mask;
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status &= 0xff;
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while (status) {
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irq = fls(status) - 1;
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generic_handle_irq(irq + start);
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status &= ~(1 << irq);
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}
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}
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static void s5pv310_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
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{
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s5pv310_irq_demux_eint(IRQ_EINT(16));
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s5pv310_irq_demux_eint(IRQ_EINT(24));
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}
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static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
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{
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u32 *irq_data = get_irq_data(irq);
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struct irq_chip *chip = get_irq_chip(irq);
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chip->mask(irq);
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if (chip->ack)
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chip->ack(irq);
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generic_handle_irq(*irq_data);
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chip->unmask(irq);
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}
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int __init s5pv310_init_irq_eint(void)
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{
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int irq;
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for (irq = 0 ; irq <= 31 ; irq++) {
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set_irq_chip(IRQ_EINT(irq), &s5pv310_irq_eint);
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set_irq_handler(IRQ_EINT(irq), handle_level_irq);
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set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
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}
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set_irq_chained_handler(IRQ_EINT16_31, s5pv310_irq_demux_eint16_31);
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for (irq = 0 ; irq <= 15 ; irq++) {
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eint0_15_data[irq] = IRQ_EINT(irq);
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set_irq_data(s5pv310_get_irq_nr(irq), &eint0_15_data[irq]);
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set_irq_chained_handler(s5pv310_get_irq_nr(irq),
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s5pv310_irq_eint0_15);
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}
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return 0;
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}
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arch_initcall(s5pv310_init_irq_eint);
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