mirror of https://gitee.com/openkylin/linux.git
ARM: dts: imx6q-utilite-pro: enable 2nd display pipeline
Apart from the already enabled Designware HDMI port, the Utilite Pro
has a second display pipeline which has the following shape:
IPU1 DI0 --> Parallel display --> tfp410 rgb24 to DVI encoder
--> HDMI connector.
Enable support for it.
In addition, since this pipeline is hardwired to IPU1, sever the link
between IPU1 and the SoC-internal Designware HDMI encoder forcing the
latter to be connected to IPU2 instead of IPU1. Otherwise, it is not
possible to drive both displays at high resolution due to the bandwidth
limitations of a single IPU.
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Christopher Spinrath
Shawn Guo
parent
d4cd158176
commit
d8f2be936c
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@ -59,6 +59,33 @@ aliases {
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rtc1 = &snvs_rtc;
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};
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encoder {
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compatible = "ti,tfp410";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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tfp410_in: endpoint {
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remote-endpoint = <¶llel_display_out>;
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};
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};
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port@1 {
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reg = <1>;
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tfp410_out: endpoint {
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remote-endpoint = <&hdmi_connector_in>;
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};
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};
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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@ -72,6 +99,19 @@ power {
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};
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};
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hdmi-connector {
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compatible = "hdmi-connector";
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type = "a";
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ddc-i2c-bus = <&i2c_dvi_ddc>;
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&tfp410_out>;
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};
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};
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};
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i2cmux {
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compatible = "i2c-mux-gpio";
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pinctrl-names = "default";
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@ -105,8 +145,46 @@ i2c_dvi_ddc: i2c@1 {
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#size-cells = <0>;
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};
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};
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parallel-display {
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compatible = "fsl,imx-parallel-display";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu1>;
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interface-pix-fmt = "rgb24";
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port@0 {
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reg = <0>;
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parallel_display_in: endpoint {
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remote-endpoint = <&ipu1_di0_disp0>;
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};
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};
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port@1 {
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reg = <1>;
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parallel_display_out: endpoint {
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remote-endpoint = <&tfp410_in>;
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};
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};
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};
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};
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/*
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* A single IPU is not able to drive both display interfaces available on the
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* Utilite Pro at high resolution due to its bandwidth limitation. Since the
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* tfp410 encoder is wired up to IPU1, sever the link between IPU1 and the
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* SoC-internal Designware HDMI encoder forcing the latter to be connected to
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* IPU2 instead of IPU1.
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*/
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/delete-node/&ipu1_di0_hdmi;
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/delete-node/&hdmi_mux_0;
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/delete-node/&ipu1_di1_hdmi;
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/delete-node/&hdmi_mux_1;
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&hdmi {
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ddc-i2c-bus = <&i2c2>;
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status = "okay";
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@ -151,6 +229,39 @@ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
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>;
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};
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pinctrl_ipu1: ipu1grp {
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fsl,pins = <
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MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38
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MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38
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MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38
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MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38
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MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38
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MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38
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MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38
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MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38
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MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38
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MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38
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MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38
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MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38
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MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38
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MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38
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MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38
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MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38
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MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38
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MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38
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MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38
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MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38
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MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38
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MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38
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MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38
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MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38
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MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38
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MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38
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MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38
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MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1
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@ -194,6 +305,10 @@ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
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};
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};
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&ipu1_di0_disp0 {
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remote-endpoint = <¶llel_display_in>;
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};
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&pcie {
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pcie@0,0 {
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reg = <0x000000 0 0 0 0>;
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