mirror of https://gitee.com/openkylin/linux.git
ARM: tegra: Fix DRAM refresh-interval clobbering on resume from LP1 on Tegra30
The DRAM refresh-interval is getting erroneously set to "1" on exiting from memory self-refreshing mode. The clobbered interval causes the "refresh request overflow timeout" error raised by the External Memory Controller on exiting from LP1 on Tegra30. The same may happen on Tegra20, but EMC registers are not latched after exiting from self-refreshing mode on Tegra20 and hence refresh-interval is not altered until an event that causes registers latching happens. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -32,7 +32,6 @@
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#define EMC_CFG 0xc
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#define EMC_ADR_CFG 0x10
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#define EMC_REFRESH 0x70
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#define EMC_NOP 0xdc
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#define EMC_SELF_REF 0xe0
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#define EMC_REQ_CTRL 0x2b0
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@ -397,7 +396,6 @@ padload_done:
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mov r1, #1
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str r1, [r0, #EMC_NOP]
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str r1, [r0, #EMC_NOP]
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str r1, [r0, #EMC_REFRESH]
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emc_device_mask r1, r0
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@ -29,7 +29,6 @@
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#define EMC_CFG 0xc
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#define EMC_ADR_CFG 0x10
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#define EMC_TIMING_CONTROL 0x28
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#define EMC_REFRESH 0x70
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#define EMC_NOP 0xdc
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#define EMC_SELF_REF 0xe0
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#define EMC_MRW 0xe8
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@ -459,7 +458,6 @@ emc_wait_auto_cal_onetime:
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cmp r10, #TEGRA30
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streq r1, [r0, #EMC_NOP]
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streq r1, [r0, #EMC_NOP]
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streq r1, [r0, #EMC_REFRESH]
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emc_device_mask r1, r0
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