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CRIS: add pgprot_noncached 

On CRIS, the high address bit controls caching, which means that
we can add a pgprot_noncached() macro that sets this bit in the
address.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
This commit is contained in:
Arnd Bergmann 2009-06-26 08:14:36 +02:00 committed by Jesper Nilsson
parent adda766193
commit d8fb91e834
3 changed files with 13 additions and 8 deletions
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9
arch/cris/include/arch-v10/arch/mmu.h
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@ -33,10 +33,10 @@ typedef struct
/* CRIS PTE bits (see R_TLB_LO in the register description) /* CRIS PTE bits (see R_TLB_LO in the register description)
* *
* Bit: 31-13 12-------4 3 2 1 0 * Bit: 31 30-13 12-------4 3 2 1 0
* ________________________________________________ * _______________________________________________________
* | pfn | reserved | global | valid | kernel | we | * | cache |pfn | reserved | global | valid | kernel | we |
* |_____|__________|________|_______|________|_____| * |_______|____|__________|________|_______|________|_____|
* *
* (pfn = physical frame number) * (pfn = physical frame number)
*/ */
@ -53,6 +53,7 @@ typedef struct
#define _PAGE_VALID (1<<2) /* page is valid */ #define _PAGE_VALID (1<<2) /* page is valid */
#define _PAGE_SILENT_READ (1<<2) /* synonym */ #define _PAGE_SILENT_READ (1<<2) /* synonym */
#define _PAGE_GLOBAL (1<<3) /* global page - context is ignored */ #define _PAGE_GLOBAL (1<<3) /* global page - context is ignored */
#define _PAGE_NO_CACHE (1<<31) /* part of the uncached memory map */
/* Bits the HW doesn't care about but the kernel uses them in SW */ /* Bits the HW doesn't care about but the kernel uses them in SW */

10
arch/cris/include/arch-v32/arch/mmu.h
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@ -28,10 +28,10 @@ typedef struct
/* /*
* CRISv32 PTE bits: * CRISv32 PTE bits:
* *
* Bit: 31-13 12-5 4 3 2 1 0 * Bit: 31 30-13 12-5 4 3 2 1 0
* +-----+------+--------+-------+--------+-------+---------+ * +-------+-----+------+--------+-------+--------+-------+---------+
* | pfn | zero | global | valid | kernel | write | execute | * | cache | pfn | zero | global | valid | kernel | write | execute |
* +-----+------+--------+-------+--------+-------+---------+ * +-------+-----+------+--------+-------+--------+-------+---------+
*/ */
/* /*
@ -45,6 +45,8 @@ typedef struct
#define _PAGE_VALID (1 << 3) /* Page is valid. */ #define _PAGE_VALID (1 << 3) /* Page is valid. */
#define _PAGE_SILENT_READ (1 << 3) /* Same as above. */ #define _PAGE_SILENT_READ (1 << 3) /* Same as above. */
#define _PAGE_GLOBAL (1 << 4) /* Global page. */ #define _PAGE_GLOBAL (1 << 4) /* Global page. */
#define _PAGE_NO_CACHE (1 << 31) /* part of the uncached memory map */
/* /*
* The hardware doesn't care about these bits, but the kernel uses them in * The hardware doesn't care about these bits, but the kernel uses them in

2
arch/cris/include/asm/pgtable.h
View File

@ -197,6 +197,8 @@ static inline pte_t __mk_pte(void * page, pgprot_t pgprot)
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; } { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) | _PAGE_NO_CACHE))
/* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval /* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval
* __pte_page(pte_val) refers to the "virtual" DRAM interval * __pte_page(pte_val) refers to the "virtual" DRAM interval