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docs: amu: supress some Sphinx warnings
Add extra blank lines on some places, in order to avoid those warnings when building the docs: Documentation/arm64/amu.rst:26: WARNING: Unexpected indentation. Documentation/arm64/amu.rst:60: WARNING: Unexpected indentation. Documentation/arm64/amu.rst:81: WARNING: Unexpected indentation. Documentation/arm64/amu.rst:108: WARNING: Unexpected indentation. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/ab0881638fc41ed790b3307a8e022ec84b7cce7e.1586881715.git.mchehab+huawei@kernel.org Signed-off-by: Jonathan Corbet <corbet@lwn.net>
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@ -23,6 +23,7 @@ optional external memory-mapped interface.
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Version 1 of the Activity Monitors architecture implements a counter group
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of four fixed and architecturally defined 64-bit event counters.
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- CPU cycle counter: increments at the frequency of the CPU.
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- Constant counter: increments at the fixed frequency of the system
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clock.
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@ -57,6 +58,7 @@ counters, only the presence of the extension.
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Firmware (code running at higher exception levels, e.g. arm-tf) support is
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needed to:
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- Enable access for lower exception levels (EL2 and EL1) to the AMU
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registers.
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- Enable the counters. If not enabled these will read as 0.
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@ -78,6 +80,7 @@ are not trapped in EL2/EL3.
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The fixed counters of AMUv1 are accessible though the following system
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register definitions:
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- SYS_AMEVCNTR0_CORE_EL0
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- SYS_AMEVCNTR0_CONST_EL0
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- SYS_AMEVCNTR0_INST_RET_EL0
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@ -93,6 +96,7 @@ Userspace access
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----------------
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Currently, access from userspace to the AMU registers is disabled due to:
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- Security reasons: they might expose information about code executed in
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secure mode.
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- Purpose: AMU counters are intended for system management use.
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@ -105,6 +109,7 @@ Virtualization
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Currently, access from userspace (EL0) and kernelspace (EL1) on the KVM
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guest side is disabled due to:
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- Security reasons: they might expose information about code executed
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by other guests or the host.
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