mirror of https://gitee.com/openkylin/linux.git
mtd: spi-nor: remove the jedec_id/ext_id
The "id" array contains all the information about the JEDEC and the manufacturer ID info. This patch removes the jedec_id/ext_id from flash_info. Signed-off-by: Huang Shijie <shijie.huang@intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit is contained in:
Huang Shijie
Brian Norris
parent
09ffafb697
commit
d928a25938
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@ -26,7 +26,38 @@
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/* Define max times to check status register before we give up. */
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#define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
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#define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
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#define SPI_NOR_MAX_ID_LEN 6
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struct flash_info {
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/*
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* This array stores the ID bytes.
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* The first three bytes are the JEDIC ID.
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* JEDEC ID zero means "no ID" (mostly older chips).
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*/
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u8 id[SPI_NOR_MAX_ID_LEN];
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u8 id_len;
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/* The size listed here is what works with SPINOR_OP_SE, which isn't
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* necessarily called a "sector" by the vendor.
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*/
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unsigned sector_size;
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u16 n_sectors;
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u16 page_size;
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u16 addr_width;
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u16 flags;
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#define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
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#define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
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#define SST_WRITE 0x04 /* use SST byte programming */
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#define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
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#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
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#define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
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#define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
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#define USE_FSR 0x80 /* use flag status register */
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};
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#define JEDEC_MFR(info) ((info)->id[0])
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static const struct spi_device_id *spi_nor_match_id(const char *name);
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@ -138,13 +169,14 @@ static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
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}
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/* Enable/disable 4-byte addressing mode. */
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static inline int set_4byte(struct spi_nor *nor, u32 jedec_id, int enable)
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static inline int set_4byte(struct spi_nor *nor, struct flash_info *info,
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int enable)
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{
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int status;
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bool need_wren = false;
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u8 cmd;
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switch (JEDEC_MFR(jedec_id)) {
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switch (JEDEC_MFR(info)) {
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case CFI_MFR_ST: /* Micron, actually */
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/* Some Micron need WREN command; all will accept it */
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need_wren = true;
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@ -418,49 +450,9 @@ static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
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return ret;
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}
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#define SPI_NOR_MAX_ID_LEN 6
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struct flash_info {
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/* JEDEC id zero means "no ID" (most older chips); otherwise it has
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* a high byte of zero plus three data bytes: the manufacturer id,
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* then a two byte device id.
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*/
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u32 jedec_id;
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u16 ext_id;
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/*
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* This array stores the ID bytes.
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* The first three bytes are the JEDIC ID.
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* JEDEC ID zero means "no ID" (mostly older chips).
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*/
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u8 id[SPI_NOR_MAX_ID_LEN];
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u8 id_len;
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/* The size listed here is what works with SPINOR_OP_SE, which isn't
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* necessarily called a "sector" by the vendor.
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*/
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unsigned sector_size;
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u16 n_sectors;
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u16 page_size;
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u16 addr_width;
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u16 flags;
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#define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
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#define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
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#define SST_WRITE 0x04 /* use SST byte programming */
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#define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
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#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
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#define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
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#define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
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#define USE_FSR 0x80 /* use flag status register */
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};
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/* Used when the "_ext_id" is two bytes at most */
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#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
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((kernel_ulong_t)&(struct flash_info) { \
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.jedec_id = (_jedec_id), \
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.ext_id = (_ext_id), \
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.id = { \
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((_jedec_id) >> 16) & 0xff, \
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((_jedec_id) >> 8) & 0xff, \
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@ -878,11 +870,11 @@ static int spansion_quad_enable(struct spi_nor *nor)
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return 0;
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}
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static int set_quad_mode(struct spi_nor *nor, u32 jedec_id)
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static int set_quad_mode(struct spi_nor *nor, struct flash_info *info)
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{
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int status;
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switch (JEDEC_MFR(jedec_id)) {
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switch (JEDEC_MFR(info)) {
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case CFI_MFR_MACRONIX:
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status = macronix_quad_enable(nor);
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if (status) {
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@ -931,7 +923,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
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info = (void *)id->driver_data;
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if (info->jedec_id) {
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if (info->id_len) {
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const struct spi_device_id *jid;
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jid = spi_nor_read_id(nor);
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@ -959,9 +951,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
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* up with the software protection bits set
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*/
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if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
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JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
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JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
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if (JEDEC_MFR(info) == CFI_MFR_ATMEL ||
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JEDEC_MFR(info) == CFI_MFR_INTEL ||
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JEDEC_MFR(info) == CFI_MFR_SST) {
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write_enable(nor);
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write_sr(nor, 0);
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}
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@ -976,7 +968,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
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mtd->_read = spi_nor_read;
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/* nor protection support for STmicro chips */
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if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
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if (JEDEC_MFR(info) == CFI_MFR_ST) {
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mtd->_lock = spi_nor_lock;
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mtd->_unlock = spi_nor_unlock;
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}
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@ -1029,7 +1021,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
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/* Quad/Dual-read mode takes precedence over fast/normal */
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if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
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ret = set_quad_mode(nor, info->jedec_id);
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ret = set_quad_mode(nor, info);
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if (ret) {
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dev_err(dev, "quad mode not supported\n");
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return ret;
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@ -1065,7 +1057,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
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else if (mtd->size > 0x1000000) {
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/* enable 4-byte addressing if the device exceeds 16MiB */
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nor->addr_width = 4;
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if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) {
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if (JEDEC_MFR(info) == CFI_MFR_AMD) {
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/* Dedicated 4-byte command set */
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switch (nor->flash_read) {
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case SPI_NOR_QUAD:
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@ -1086,7 +1078,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
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nor->erase_opcode = SPINOR_OP_SE_4B;
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mtd->erasesize = info->sector_size;
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} else
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set_4byte(nor, info->jedec_id, 1);
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set_4byte(nor, info, 1);
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} else {
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nor->addr_width = 3;
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}
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