mirror of https://gitee.com/openkylin/linux.git
dt-bindings: clock: renesas: cpg: Convert to json-schema
Convert the Renesas Clock Pulse Generator (CPG) Device Tree binding documentation to json-schema, combining support for: - R-Mobile APE6 (R8A73A4) and A1 (R8A7740), - R-Car M1 (R8A7778) and H1 (R8A7779), - RZ/A1 (R7S72100), - SH-Mobile AG5 (SH73A0). Keep the example for R-Mobile A1, which shows most properties. Drop the consumer examples, as they do not belong here. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200518081644.23683-1-geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas Clock Pulse Generator (CPG)
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description:
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The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
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includes PLLs, and fixed and variable ratio dividers.
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The CPG may also provide a Clock Domain for SoC devices, in combination with
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the CPG Module Stop (MSTP) Clocks.
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properties:
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compatible:
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oneOf:
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- const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
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- const: renesas,r8a7740-cpg-clocks # R-Mobile A1
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- const: renesas,r8a7778-cpg-clocks # R-Car M1
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- const: renesas,r8a7779-cpg-clocks # R-Car H1
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- items:
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- enum:
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- renesas,r7s72100-cpg-clocks # RZ/A1H
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- const: renesas,rz-cpg-clocks # RZ/A1
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- const: renesas,sh73a0-cpg-clocks # SH-Mobile AG5
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reg:
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maxItems: 1
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clocks: true
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'#clock-cells':
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const: 1
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clock-output-names: true
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renesas,mode:
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description: Board-specific settings of the MD_CK* bits on R-Mobile A1
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 7
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'#power-domain-cells':
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const: 0
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- clock-output-names
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r8a73a4-cpg-clocks
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then:
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properties:
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clocks:
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items:
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- description: extal1
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- description: extal2
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clock-output-names:
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items:
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- const: main
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- const: pll0
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- const: pll1
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- const: pll2
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- const: pll2s
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- const: pll2h
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- const: z
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- const: z2
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- const: i
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- const: m3
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- const: b
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- const: m1
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- const: m2
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- const: zx
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- const: zs
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- const: hp
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r8a7740-cpg-clocks
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then:
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properties:
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clocks:
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items:
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- description: extal1
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- description: extal2
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- description: extalr
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clock-output-names:
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items:
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- const: system
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- const: pllc0
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- const: pllc1
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- const: pllc2
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- const: r
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- const: usb24s
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- const: i
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- const: zg
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- const: b
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- const: m1
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- const: hp
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- const: hpp
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- const: usbp
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- const: s
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- const: zb
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- const: m3
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- const: cp
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required:
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- renesas,mode
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r8a7778-cpg-clocks
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then:
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properties:
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clocks:
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maxItems: 1
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clock-output-names:
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items:
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- const: plla
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- const: pllb
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- const: b
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- const: out
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- const: p
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- const: s
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- const: s1
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r8a7779-cpg-clocks
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then:
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properties:
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clocks:
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maxItems: 1
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clock-output-names:
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items:
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- const: plla
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- const: z
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- const: zs
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- const: s
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- const: s1
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- const: p
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- const: b
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- const: out
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r7s72100-cpg-clocks
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then:
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properties:
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clocks:
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items:
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- description: extal1
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- description: usb_x1
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clock-output-names:
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items:
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- const: pll
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- const: i
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- const: g
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- if:
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properties:
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compatible:
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contains:
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const: renesas,sh73a0-cpg-clocks
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then:
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properties:
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clocks:
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items:
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- description: extal1
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- description: extal2
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clock-output-names:
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items:
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- const: main
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- const: pll0
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- const: pll1
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- const: pll2
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- const: pll3
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- const: dsi0phy
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- const: dsi1phy
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- const: zg
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- const: m3
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- const: b
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- const: m1
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- const: m2
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- const: z
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- const: zx
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- const: hp
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- if:
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properties:
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compatible:
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contains:
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enum:
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- renesas,r8a7778-cpg-clocks
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- renesas,r8a7779-cpg-clocks
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- renesas,rz-cpg-clocks
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then:
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required:
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r8a7740-clock.h>
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a7740-cpg-clocks";
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reg = <0xe6150000 0x10000>;
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clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
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#clock-cells = <1>;
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clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",
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"usb24s", "i", "zg", "b", "m1", "hp", "hpp",
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"usbp", "s", "zb", "m3", "cp";
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renesas,mode = <0x05>;
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};
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@ -1,33 +0,0 @@
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* Renesas R8A73A4 Clock Pulse Generator (CPG)
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The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs
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and several fixed ratio dividers.
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Required Properties:
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- compatible: Must be "renesas,r8a73a4-cpg-clocks"
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- reg: Base address and length of the memory resource used by the CPG
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- clocks: Reference to the parent clocks ("extal1" and "extal2")
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are "main",
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"pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
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"m1", "m2", "zx", "zs", and "hp".
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Example
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-------
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a73a4-cpg-clocks";
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reg = <0 0xe6150000 0 0x10000>;
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clocks = <&extal1_clk>, <&extal2_clk>;
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#clock-cells = <1>;
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clock-output-names = "main", "pll0", "pll1", "pll2",
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"pll2s", "pll2h", "z", "z2",
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"i", "m3", "b", "m1", "m2",
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"zx", "zs", "hp";
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};
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@ -1,41 +0,0 @@
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These bindings should be considered EXPERIMENTAL for now.
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* Renesas R8A7740 Clock Pulse Generator (CPG)
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The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs
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and several fixed ratio and variable ratio dividers.
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Required Properties:
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- compatible: Must be "renesas,r8a7740-cpg-clocks"
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- reg: Base address and length of the memory resource used by the CPG
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- clocks: Reference to the three parent clocks
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are
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"system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b",
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"m1", "hp", "hpp", "usbp", "s", "zb", "m3", and "cp".
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- renesas,mode: board-specific settings of the MD_CK* bits
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Example
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-------
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a7740-cpg-clocks";
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reg = <0xe6150000 0x10000>;
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clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
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#clock-cells = <1>;
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clock-output-names = "system", "pllc0", "pllc1",
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"pllc2", "r",
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"usb24s",
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"i", "zg", "b", "m1", "hp",
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"hpp", "usbp", "s", "zb", "m3",
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"cp";
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};
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&cpg_clocks {
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renesas,mode = <0x05>;
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};
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@ -1,47 +0,0 @@
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* Renesas R8A7778 Clock Pulse Generator (CPG)
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The CPG generates core clocks for the R8A7778. It includes two PLLs and
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several fixed ratio dividers.
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The CPG also provides a Clock Domain for SoC devices, in combination with the
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CPG Module Stop (MSTP) Clocks.
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Required Properties:
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- compatible: Must be "renesas,r8a7778-cpg-clocks"
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- reg: Base address and length of the memory resource used by the CPG
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are
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"plla", "pllb", "b", "out", "p", "s", and "s1".
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- #power-domain-cells: Must be 0
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SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
|
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through an MSTP clock should refer to the CPG device node in their
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"power-domains" property, as documented by the generic PM domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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Examples
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--------
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- CPG device node:
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cpg_clocks: cpg_clocks@ffc80000 {
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compatible = "renesas,r8a7778-cpg-clocks";
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reg = <0xffc80000 0x80>;
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#clock-cells = <1>;
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clocks = <&extal_clk>;
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clock-output-names = "plla", "pllb", "b",
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"out", "p", "s", "s1";
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#power-domain-cells = <0>;
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};
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- CPG/MSTP Clock Domain member device node:
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sdhi0: sd@ffe4c000 {
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compatible = "renesas,sdhi-r8a7778";
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reg = <0xffe4c000 0x100>;
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interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
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power-domains = <&cpg_clocks>;
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};
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@ -1,49 +0,0 @@
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* Renesas R8A7779 Clock Pulse Generator (CPG)
|
|
||||||
|
|
||||||
The CPG generates core clocks for the R8A7779. It includes one PLL and
|
|
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several fixed ratio dividers.
|
|
||||||
The CPG also provides a Clock Domain for SoC devices, in combination with the
|
|
||||||
CPG Module Stop (MSTP) Clocks.
|
|
||||||
|
|
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Required Properties:
|
|
||||||
|
|
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- compatible: Must be "renesas,r8a7779-cpg-clocks"
|
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- reg: Base address and length of the memory resource used by the CPG
|
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- clocks: Reference to the parent clock
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are "plla",
|
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"z", "zs", "s", "s1", "p", "b", "out".
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- #power-domain-cells: Must be 0
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SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
|
|
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through an MSTP clock should refer to the CPG device node in their
|
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"power-domains" property, as documented by the generic PM domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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Examples
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--------
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||||||
- CPG device node:
|
|
||||||
|
|
||||||
cpg_clocks: cpg_clocks@ffc80000 {
|
|
||||||
compatible = "renesas,r8a7779-cpg-clocks";
|
|
||||||
reg = <0xffc80000 0x30>;
|
|
||||||
clocks = <&extal_clk>;
|
|
||||||
#clock-cells = <1>;
|
|
||||||
clock-output-names = "plla", "z", "zs", "s", "s1", "p",
|
|
||||||
"b", "out";
|
|
||||||
#power-domain-cells = <0>;
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
- CPG/MSTP Clock Domain member device node:
|
|
||||||
|
|
||||||
sata: sata@fc600000 {
|
|
||||||
compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
|
|
||||||
reg = <0xfc600000 0x2000>;
|
|
||||||
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&mstp1_clks R8A7779_CLK_SATA>;
|
|
||||||
power-domains = <&cpg_clocks>;
|
|
||||||
};
|
|
||||||
|
|
@ -1,53 +0,0 @@
|
||||||
* Renesas RZ/A1 Clock Pulse Generator (CPG)
|
|
||||||
|
|
||||||
The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable
|
|
||||||
CPU and GPU clocks, and several fixed ratio dividers.
|
|
||||||
The CPG also provides a Clock Domain for SoC devices, in combination with the
|
|
||||||
CPG Module Stop (MSTP) Clocks.
|
|
||||||
|
|
||||||
Required Properties:
|
|
||||||
|
|
||||||
- compatible: Must be one of
|
|
||||||
- "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
|
|
||||||
and "renesas,rz-cpg-clocks" as a fallback.
|
|
||||||
- reg: Base address and length of the memory resource used by the CPG
|
|
||||||
- clocks: References to possible parent clocks. Order must match clock modes
|
|
||||||
in the datasheet. For the r7s72100, this is extal, usb_x1.
|
|
||||||
- #clock-cells: Must be 1
|
|
||||||
- clock-output-names: The names of the clocks. Supported clocks are "pll",
|
|
||||||
"i", and "g"
|
|
||||||
- #power-domain-cells: Must be 0
|
|
||||||
|
|
||||||
SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
|
|
||||||
through an MSTP clock should refer to the CPG device node in their
|
|
||||||
"power-domains" property, as documented by the generic PM domain bindings in
|
|
||||||
Documentation/devicetree/bindings/power/power_domain.txt.
|
|
||||||
|
|
||||||
|
|
||||||
Examples
|
|
||||||
--------
|
|
||||||
|
|
||||||
- CPG device node:
|
|
||||||
|
|
||||||
cpg_clocks: cpg_clocks@fcfe0000 {
|
|
||||||
#clock-cells = <1>;
|
|
||||||
compatible = "renesas,r7s72100-cpg-clocks",
|
|
||||||
"renesas,rz-cpg-clocks";
|
|
||||||
reg = <0xfcfe0000 0x18>;
|
|
||||||
clocks = <&extal_clk>, <&usb_x1_clk>;
|
|
||||||
clock-output-names = "pll", "i", "g";
|
|
||||||
#power-domain-cells = <0>;
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
- CPG/MSTP Clock Domain member device node:
|
|
||||||
|
|
||||||
mtu2: timer@fcff0000 {
|
|
||||||
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
|
|
||||||
reg = <0xfcff0000 0x400>;
|
|
||||||
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
interrupt-names = "tgi0a";
|
|
||||||
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
|
|
||||||
clock-names = "fck";
|
|
||||||
power-domains = <&cpg_clocks>;
|
|
||||||
};
|
|
||||||
|
|
@ -1,35 +0,0 @@
|
||||||
These bindings should be considered EXPERIMENTAL for now.
|
|
||||||
|
|
||||||
* Renesas SH73A0 Clock Pulse Generator (CPG)
|
|
||||||
|
|
||||||
The CPG generates core clocks for the SH73A0 SoC. It includes four PLLs
|
|
||||||
and several fixed ratio dividers.
|
|
||||||
|
|
||||||
Required Properties:
|
|
||||||
|
|
||||||
- compatible: Must be "renesas,sh73a0-cpg-clocks"
|
|
||||||
|
|
||||||
- reg: Base address and length of the memory resource used by the CPG
|
|
||||||
|
|
||||||
- clocks: Reference to the parent clocks ("extal1" and "extal2")
|
|
||||||
|
|
||||||
- #clock-cells: Must be 1
|
|
||||||
|
|
||||||
- clock-output-names: The names of the clocks. Supported clocks are "main",
|
|
||||||
"pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
|
|
||||||
"m1", "m2", "z", "zx", and "hp".
|
|
||||||
|
|
||||||
|
|
||||||
Example
|
|
||||||
-------
|
|
||||||
|
|
||||||
cpg_clocks: cpg_clocks@e6150000 {
|
|
||||||
compatible = "renesas,sh73a0-cpg-clocks";
|
|
||||||
reg = <0 0xe6150000 0 0x10000>;
|
|
||||||
clocks = <&extal1_clk>, <&extal2_clk>;
|
|
||||||
#clock-cells = <1>;
|
|
||||||
clock-output-names = "main", "pll0", "pll1", "pll2",
|
|
||||||
"pll3", "dsi0phy", "dsi1phy",
|
|
||||||
"zg", "m3", "b", "m1", "m2",
|
|
||||||
"z", "zx", "hp";
|
|
||||||
};
|
|
||||||
Loading…
Reference in New Issue