mirror of https://gitee.com/openkylin/linux.git
dt-bindings: clock: renesas: cpg: Convert to json-schema
Convert the Renesas Clock Pulse Generator (CPG) Device Tree binding documentation to json-schema, combining support for: - R-Mobile APE6 (R8A73A4) and A1 (R8A7740), - R-Car M1 (R8A7778) and H1 (R8A7779), - RZ/A1 (R7S72100), - SH-Mobile AG5 (SH73A0). Keep the example for R-Mobile A1, which shows most properties. Drop the consumer examples, as they do not belong here. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200518081644.23683-1-geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven
parent
b3a9e3b962
commit
d9563c972c
|
|
@ -0,0 +1,241 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas Clock Pulse Generator (CPG)
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
description:
|
||||
The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
|
||||
includes PLLs, and fixed and variable ratio dividers.
|
||||
|
||||
The CPG may also provide a Clock Domain for SoC devices, in combination with
|
||||
the CPG Module Stop (MSTP) Clocks.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
|
||||
- const: renesas,r8a7740-cpg-clocks # R-Mobile A1
|
||||
- const: renesas,r8a7778-cpg-clocks # R-Car M1
|
||||
- const: renesas,r8a7779-cpg-clocks # R-Car H1
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,r7s72100-cpg-clocks # RZ/A1H
|
||||
- const: renesas,rz-cpg-clocks # RZ/A1
|
||||
- const: renesas,sh73a0-cpg-clocks # SH-Mobile AG5
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks: true
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clock-output-names: true
|
||||
|
||||
renesas,mode:
|
||||
description: Board-specific settings of the MD_CK* bits on R-Mobile A1
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- clock-output-names
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,r8a73a4-cpg-clocks
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: extal1
|
||||
- description: extal2
|
||||
|
||||
clock-output-names:
|
||||
items:
|
||||
- const: main
|
||||
- const: pll0
|
||||
- const: pll1
|
||||
- const: pll2
|
||||
- const: pll2s
|
||||
- const: pll2h
|
||||
- const: z
|
||||
- const: z2
|
||||
- const: i
|
||||
- const: m3
|
||||
- const: b
|
||||
- const: m1
|
||||
- const: m2
|
||||
- const: zx
|
||||
- const: zs
|
||||
- const: hp
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,r8a7740-cpg-clocks
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: extal1
|
||||
- description: extal2
|
||||
- description: extalr
|
||||
|
||||
clock-output-names:
|
||||
items:
|
||||
- const: system
|
||||
- const: pllc0
|
||||
- const: pllc1
|
||||
- const: pllc2
|
||||
- const: r
|
||||
- const: usb24s
|
||||
- const: i
|
||||
- const: zg
|
||||
- const: b
|
||||
- const: m1
|
||||
- const: hp
|
||||
- const: hpp
|
||||
- const: usbp
|
||||
- const: s
|
||||
- const: zb
|
||||
- const: m3
|
||||
- const: cp
|
||||
|
||||
required:
|
||||
- renesas,mode
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,r8a7778-cpg-clocks
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
items:
|
||||
- const: plla
|
||||
- const: pllb
|
||||
- const: b
|
||||
- const: out
|
||||
- const: p
|
||||
- const: s
|
||||
- const: s1
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,r8a7779-cpg-clocks
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
items:
|
||||
- const: plla
|
||||
- const: z
|
||||
- const: zs
|
||||
- const: s
|
||||
- const: s1
|
||||
- const: p
|
||||
- const: b
|
||||
- const: out
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,r7s72100-cpg-clocks
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: extal1
|
||||
- description: usb_x1
|
||||
|
||||
clock-output-names:
|
||||
items:
|
||||
- const: pll
|
||||
- const: i
|
||||
- const: g
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,sh73a0-cpg-clocks
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: extal1
|
||||
- description: extal2
|
||||
|
||||
clock-output-names:
|
||||
items:
|
||||
- const: main
|
||||
- const: pll0
|
||||
- const: pll1
|
||||
- const: pll2
|
||||
- const: pll3
|
||||
- const: dsi0phy
|
||||
- const: dsi1phy
|
||||
- const: zg
|
||||
- const: m3
|
||||
- const: b
|
||||
- const: m1
|
||||
- const: m2
|
||||
- const: z
|
||||
- const: zx
|
||||
- const: hp
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,r8a7778-cpg-clocks
|
||||
- renesas,r8a7779-cpg-clocks
|
||||
- renesas,rz-cpg-clocks
|
||||
then:
|
||||
required:
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a7740-clock.h>
|
||||
cpg_clocks: cpg_clocks@e6150000 {
|
||||
compatible = "renesas,r8a7740-cpg-clocks";
|
||||
reg = <0xe6150000 0x10000>;
|
||||
clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",
|
||||
"usb24s", "i", "zg", "b", "m1", "hp", "hpp",
|
||||
"usbp", "s", "zb", "m3", "cp";
|
||||
renesas,mode = <0x05>;
|
||||
};
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
* Renesas R8A73A4 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs
|
||||
and several fixed ratio dividers.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "renesas,r8a73a4-cpg-clocks"
|
||||
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
|
||||
- clocks: Reference to the parent clocks ("extal1" and "extal2")
|
||||
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
- clock-output-names: The names of the clocks. Supported clocks are "main",
|
||||
"pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
|
||||
"m1", "m2", "zx", "zs", and "hp".
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
cpg_clocks: cpg_clocks@e6150000 {
|
||||
compatible = "renesas,r8a73a4-cpg-clocks";
|
||||
reg = <0 0xe6150000 0 0x10000>;
|
||||
clocks = <&extal1_clk>, <&extal2_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "main", "pll0", "pll1", "pll2",
|
||||
"pll2s", "pll2h", "z", "z2",
|
||||
"i", "m3", "b", "m1", "m2",
|
||||
"zx", "zs", "hp";
|
||||
};
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
These bindings should be considered EXPERIMENTAL for now.
|
||||
|
||||
* Renesas R8A7740 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs
|
||||
and several fixed ratio and variable ratio dividers.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "renesas,r8a7740-cpg-clocks"
|
||||
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
|
||||
- clocks: Reference to the three parent clocks
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The names of the clocks. Supported clocks are
|
||||
"system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b",
|
||||
"m1", "hp", "hpp", "usbp", "s", "zb", "m3", and "cp".
|
||||
|
||||
- renesas,mode: board-specific settings of the MD_CK* bits
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
cpg_clocks: cpg_clocks@e6150000 {
|
||||
compatible = "renesas,r8a7740-cpg-clocks";
|
||||
reg = <0xe6150000 0x10000>;
|
||||
clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "system", "pllc0", "pllc1",
|
||||
"pllc2", "r",
|
||||
"usb24s",
|
||||
"i", "zg", "b", "m1", "hp",
|
||||
"hpp", "usbp", "s", "zb", "m3",
|
||||
"cp";
|
||||
};
|
||||
|
||||
&cpg_clocks {
|
||||
renesas,mode = <0x05>;
|
||||
};
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
* Renesas R8A7778 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the R8A7778. It includes two PLLs and
|
||||
several fixed ratio dividers.
|
||||
The CPG also provides a Clock Domain for SoC devices, in combination with the
|
||||
CPG Module Stop (MSTP) Clocks.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "renesas,r8a7778-cpg-clocks"
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The names of the clocks. Supported clocks are
|
||||
"plla", "pllb", "b", "out", "p", "s", and "s1".
|
||||
- #power-domain-cells: Must be 0
|
||||
|
||||
SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
|
||||
through an MSTP clock should refer to the CPG device node in their
|
||||
"power-domains" property, as documented by the generic PM domain bindings in
|
||||
Documentation/devicetree/bindings/power/power_domain.txt.
|
||||
|
||||
|
||||
Examples
|
||||
--------
|
||||
|
||||
- CPG device node:
|
||||
|
||||
cpg_clocks: cpg_clocks@ffc80000 {
|
||||
compatible = "renesas,r8a7778-cpg-clocks";
|
||||
reg = <0xffc80000 0x80>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&extal_clk>;
|
||||
clock-output-names = "plla", "pllb", "b",
|
||||
"out", "p", "s", "s1";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
|
||||
- CPG/MSTP Clock Domain member device node:
|
||||
|
||||
sdhi0: sd@ffe4c000 {
|
||||
compatible = "renesas,sdhi-r8a7778";
|
||||
reg = <0xffe4c000 0x100>;
|
||||
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
|
@ -1,49 +0,0 @@
|
|||
* Renesas R8A7779 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the R8A7779. It includes one PLL and
|
||||
several fixed ratio dividers.
|
||||
The CPG also provides a Clock Domain for SoC devices, in combination with the
|
||||
CPG Module Stop (MSTP) Clocks.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "renesas,r8a7779-cpg-clocks"
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
|
||||
- clocks: Reference to the parent clock
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The names of the clocks. Supported clocks are "plla",
|
||||
"z", "zs", "s", "s1", "p", "b", "out".
|
||||
- #power-domain-cells: Must be 0
|
||||
|
||||
SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
|
||||
through an MSTP clock should refer to the CPG device node in their
|
||||
"power-domains" property, as documented by the generic PM domain bindings in
|
||||
Documentation/devicetree/bindings/power/power_domain.txt.
|
||||
|
||||
|
||||
Examples
|
||||
--------
|
||||
|
||||
- CPG device node:
|
||||
|
||||
cpg_clocks: cpg_clocks@ffc80000 {
|
||||
compatible = "renesas,r8a7779-cpg-clocks";
|
||||
reg = <0xffc80000 0x30>;
|
||||
clocks = <&extal_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "plla", "z", "zs", "s", "s1", "p",
|
||||
"b", "out";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
|
||||
- CPG/MSTP Clock Domain member device node:
|
||||
|
||||
sata: sata@fc600000 {
|
||||
compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
|
||||
reg = <0xfc600000 0x2000>;
|
||||
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7779_CLK_SATA>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
|
@ -1,53 +0,0 @@
|
|||
* Renesas RZ/A1 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable
|
||||
CPU and GPU clocks, and several fixed ratio dividers.
|
||||
The CPG also provides a Clock Domain for SoC devices, in combination with the
|
||||
CPG Module Stop (MSTP) Clocks.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be one of
|
||||
- "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
|
||||
and "renesas,rz-cpg-clocks" as a fallback.
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
- clocks: References to possible parent clocks. Order must match clock modes
|
||||
in the datasheet. For the r7s72100, this is extal, usb_x1.
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The names of the clocks. Supported clocks are "pll",
|
||||
"i", and "g"
|
||||
- #power-domain-cells: Must be 0
|
||||
|
||||
SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
|
||||
through an MSTP clock should refer to the CPG device node in their
|
||||
"power-domains" property, as documented by the generic PM domain bindings in
|
||||
Documentation/devicetree/bindings/power/power_domain.txt.
|
||||
|
||||
|
||||
Examples
|
||||
--------
|
||||
|
||||
- CPG device node:
|
||||
|
||||
cpg_clocks: cpg_clocks@fcfe0000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "renesas,r7s72100-cpg-clocks",
|
||||
"renesas,rz-cpg-clocks";
|
||||
reg = <0xfcfe0000 0x18>;
|
||||
clocks = <&extal_clk>, <&usb_x1_clk>;
|
||||
clock-output-names = "pll", "i", "g";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
|
||||
- CPG/MSTP Clock Domain member device node:
|
||||
|
||||
mtu2: timer@fcff0000 {
|
||||
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
|
||||
reg = <0xfcff0000 0x400>;
|
||||
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tgi0a";
|
||||
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
These bindings should be considered EXPERIMENTAL for now.
|
||||
|
||||
* Renesas SH73A0 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the SH73A0 SoC. It includes four PLLs
|
||||
and several fixed ratio dividers.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "renesas,sh73a0-cpg-clocks"
|
||||
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
|
||||
- clocks: Reference to the parent clocks ("extal1" and "extal2")
|
||||
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
- clock-output-names: The names of the clocks. Supported clocks are "main",
|
||||
"pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
|
||||
"m1", "m2", "z", "zx", and "hp".
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
cpg_clocks: cpg_clocks@e6150000 {
|
||||
compatible = "renesas,sh73a0-cpg-clocks";
|
||||
reg = <0 0xe6150000 0 0x10000>;
|
||||
clocks = <&extal1_clk>, <&extal2_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "main", "pll0", "pll1", "pll2",
|
||||
"pll3", "dsi0phy", "dsi1phy",
|
||||
"zg", "m3", "b", "m1", "m2",
|
||||
"z", "zx", "hp";
|
||||
};
|
||||
Loading…
Reference in New Issue