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Renesas ARM Based SoC DT Fixes for v4.8 

* Corrections to r8a7792
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJXjDuJAAoJENfPZGlqN0++zTwP/izl3NeRBX9cz+sTDYKb9lB5
 w2OMwUE7p4aC5iFej7CmLLvhgtpC/6RJiD61F6LqHJF3GG5CJrzXo69EYrnU13R2
 4oIEZLdnWawAbAIhzKHvypgXw+6el4X3NSX29yZziVkObWxDczCYKQBNYOhzwRQd
 itoJk6oYOwgUUCkbDY9CfPyym0rHtQ/CXPxL49MZgiKX0Qkq0QyCeT4OC3XGbyu2
 1oJfBDew3i7OQnd+RirmMlVZpHBaDgIKehaUTd1ZNJomAxBuaISpdfmiliU46VcB
 6+LXBTM0LRqIvZTsdEEWd4hvMTC5A4MPb3zTel1lUeucfQrkfKIMfijBt/nNokkG
 vpGQBdCM9FuSXKylAcToFKLKi6AMaXy2dUTi8/fQcNE59VHghrB3eLHPJDRbxkCm
 2CVQ2Kjtjm+Egd+ElYsCkFXtiRqR1xFMIM2HFfGq50GFpR9KF3vwelgSgnQbO9ei
 g9qjNAuoIEJR2o+kj6XKTjGU9qRNC6DoxZLIsg32cUP8E95wU9xWfQaHbWEGUdhh
 kEQkwvVrHsLM6b3ElAj/U7cwK7AI5nDnNucOwbBM6f9XoAeVbgrTy2cz4wDfmfoR
 5lNTuyrLCv0cu0SPOHXgqPti6bxPnzYF7G/Xnm9WbJeJYnA0q2VK+4jl8ItjjgoA
 /0nNwVDhCUVCzX95Vw5g
 =BHVI
 -----END PGP SIGNATURE-----

Merge tag 'renesas-dt-fixes-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Merge "Renesas ARM Based SoC DT Fixes for v4.8" from Simon Horman:

* Corrections to r8a7792

* tag 'renesas-dt-fixes-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: dts: r8a7792: remove ADSP clock
  ARM: dts: r8a7792: add PLL1 divided by 2 clock
This commit is contained in:
Arnd Bergmann 2016-07-21 14:40:28 +02:00
parent 1b2d8b94c8 e0c3f92a08
commit d95eabc7b8
2 changed files with 8 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
arch/arm/boot/dts/r8a7792.dtsi
View File

@ -279,11 +279,18 @@ cpg_clocks: cpg_clocks@e6150000 {
clocks = <&extal_clk>;
#clock-cells = <1>;
clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "z", "adsp";
"lb", "qspi", "z";
#power-domain-cells = <0>;
};
/* Fixed factor clocks */
pll1_div2_clk: pll1_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
};
zs_clk: zs {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;

1
include/dt-bindings/clock/r8a7792-clock.h
View File

@ -18,7 +18,6 @@
#define R8A7792_CLK_LB 4
#define R8A7792_CLK_QSPI 5
#define R8A7792_CLK_Z 6
#define R8A7792_CLK_ADSP 7
/* MSTP0 */
#define R8A7792_CLK_MSIOF0 0