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ARM: versatile: rename and comment SMP implementation
Rename pen_release and boot_lock in the Versatile specific SMP implementation, describe why these exist and state clearly that they should not be used in production implementations. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Russell King
parent
830eec2467
commit
d9b778e7bf
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@ -37,5 +37,5 @@ pen: ldr r7, [r6]
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.align
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1: .long .
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.long pen_release
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.long versatile_cpu_release
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ENDPROC(versatile_secondary_startup)
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@ -18,6 +18,8 @@
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#include <asm/smp_plat.h>
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#include <asm/cp15.h>
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#include <plat/platsmp.h>
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static inline void versatile_immitation_enter_lowpower(unsigned int actrl_mask)
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{
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unsigned int v;
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@ -67,7 +69,7 @@ static inline void versatile_immitation_do_lowpower(unsigned int cpu, int *spuri
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for (;;) {
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wfi();
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if (pen_release == cpu_logical_map(cpu)) {
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if (versatile_cpu_release == cpu_logical_map(cpu)) {
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/*
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* OK, proper wakeup, we're done
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*/
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@ -8,6 +8,7 @@
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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extern volatile int versatile_cpu_release;
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extern void versatile_secondary_startup(void);
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extern void versatile_secondary_init(unsigned int cpu);
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@ -7,6 +7,11 @@
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This code is specific to the hardware found on ARM Realview and
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* Versatile Express platforms where the CPUs are unable to be individually
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* woken, and where there is no way to hot-unplug CPUs. Real platforms
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* should not copy this code.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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@ -21,18 +26,32 @@
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#include <plat/platsmp.h>
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/*
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* Write pen_release in a way that is guaranteed to be visible to all
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* observers, irrespective of whether they're taking part in coherency
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* versatile_cpu_release controls the release of CPUs from the holding
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* pen in headsmp.S, which exists because we are not always able to
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* control the release of individual CPUs from the board firmware.
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* Production platforms do not need this.
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*/
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volatile int versatile_cpu_release = -1;
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/*
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* Write versatile_cpu_release in a way that is guaranteed to be visible to
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* all observers, irrespective of whether they're taking part in coherency
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* or not. This is necessary for the hotplug code to work reliably.
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*/
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static void write_pen_release(int val)
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static void versatile_write_cpu_release(int val)
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{
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pen_release = val;
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versatile_cpu_release = val;
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smp_wmb();
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sync_cache_w(&pen_release);
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sync_cache_w(&versatile_cpu_release);
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}
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static DEFINE_RAW_SPINLOCK(boot_lock);
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/*
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* versatile_lock exists to avoid running the loops_per_jiffy delay loop
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* calibrations on the secondary CPU while the requesting CPU is using
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* the limited-bandwidth bus - which affects the calibration value.
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* Production platforms do not need this.
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*/
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static DEFINE_RAW_SPINLOCK(versatile_lock);
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void versatile_secondary_init(unsigned int cpu)
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{
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@ -40,13 +59,13 @@ void versatile_secondary_init(unsigned int cpu)
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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write_pen_release(-1);
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versatile_write_cpu_release(-1);
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/*
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* Synchronise with the boot thread.
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*/
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raw_spin_lock(&boot_lock);
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raw_spin_unlock(&boot_lock);
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raw_spin_lock(&versatile_lock);
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raw_spin_unlock(&versatile_lock);
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}
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int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
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@ -57,7 +76,7 @@ int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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raw_spin_lock(&boot_lock);
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raw_spin_lock(&versatile_lock);
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/*
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* This is really belt and braces; we hold unintended secondary
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@ -65,7 +84,7 @@ int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
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* since we haven't sent them a soft interrupt, they shouldn't
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* be there.
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*/
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write_pen_release(cpu_logical_map(cpu));
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versatile_write_cpu_release(cpu_logical_map(cpu));
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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@ -77,7 +96,7 @@ int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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if (pen_release == -1)
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if (versatile_cpu_release == -1)
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break;
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udelay(10);
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@ -87,7 +106,7 @@ int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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raw_spin_unlock(&boot_lock);
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raw_spin_unlock(&versatile_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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return versatile_cpu_release != -1 ? -ENOSYS : 0;
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}
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