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drm/i915/skl: Correcting the flushing of pipe 

We were incorreectly bypassing the flush everytime which led to fifo
underrun when more than one plane is enabled.

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Satheeshakrishna M<satheeshakrishna.m@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Sonika Jindal 2014-12-11 17:58:15 +05:30 committed by Daniel Vetter
parent 27401d126b
commit d9d8e6b3c0
1 changed files with 1 additions and 2 deletions
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3
drivers/gpu/drm/i915/intel_pm.c
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@ -3004,9 +3004,8 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
skl_wm_flush_pipe(dev_priv, pipe, 2);
intel_wait_for_vblank(dev, pipe);
reallocated[pipe] = true;
}
reallocated[pipe] = true;
}
/*