mirror of https://gitee.com/openkylin/linux.git
spi/xilinx: Do not inhibit transmission in polling mode
When no irq is used, there is no need to inhibit the transmission for every transaction. This inhibition was implemented to avoid a race condition with the irq handler. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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5fe11cc09c
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@ -163,6 +163,7 @@ static void xspi_rx32(struct xilinx_spi *xspi)
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static void xspi_init_hw(struct xilinx_spi *xspi)
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{
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void __iomem *regs_base = xspi->regs;
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u32 inhibit;
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/* Reset the SPI device */
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xspi->write_fn(XIPIF_V123B_RESET_MASK,
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@ -173,16 +174,19 @@ static void xspi_init_hw(struct xilinx_spi *xspi)
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xspi->write_fn(XSPI_INTR_TX_EMPTY,
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regs_base + XIPIF_V123B_IIER_OFFSET);
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/* Enable the global IPIF interrupt */
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if (xspi->irq >= 0)
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if (xspi->irq >= 0) {
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xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
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regs_base + XIPIF_V123B_DGIER_OFFSET);
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else
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inhibit = XSPI_CR_TRANS_INHIBIT;
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} else {
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xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
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inhibit = 0;
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}
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/* Deselect the slave on the SPI bus */
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xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
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/* Disable the transmitter, enable Manual Slave Select Assertion,
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* put SPI controller into master mode, and enable it */
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xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT |
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xspi->write_fn(inhibit | XSPI_CR_MANUAL_SSELECT |
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XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET |
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XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET);
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}
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@ -252,7 +256,7 @@ static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
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reinit_completion(&xspi->done);
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while (xspi->remaining_bytes) {
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u16 cr;
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u16 cr = 0;
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int n_words;
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n_words = (xspi->remaining_bytes * 8) / xspi->bits_per_word;
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@ -263,13 +267,13 @@ static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
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/* Start the transfer by not inhibiting the transmitter any
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* longer
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*/
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cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
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~XSPI_CR_TRANS_INHIBIT;
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xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
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if (xspi->irq >= 0)
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if (xspi->irq >= 0) {
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cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
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~XSPI_CR_TRANS_INHIBIT;
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xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
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wait_for_completion(&xspi->done);
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else
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} else
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while (!(xspi->read_fn(xspi->regs + XSPI_SR_OFFSET) &
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XSPI_SR_TX_EMPTY_MASK))
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;
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@ -279,7 +283,8 @@ static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
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* transmitter while the Isr refills the transmit register/FIFO,
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* or make sure it is stopped if we're done.
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*/
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xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
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if (xspi->irq >= 0)
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xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
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xspi->regs + XSPI_CR_OFFSET);
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/* Read out all the data from the Rx FIFO */
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