mirror of https://gitee.com/openkylin/linux.git
ARM: shmobile: r8a7740: add SoC clocks to DTS
Declares the r8a7740 clocks supported by the legacy clock framework, excluding those requiring extensions to the DIV6 driver. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Ulrich Hecht
Simon Horman
parent
477fa2bc4c
commit
d9ffd583bf
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@ -10,6 +10,7 @@
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/include/ "skeleton.dtsi"
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#include <dt-bindings/clock/r8a7740-clock.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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@ -291,4 +292,183 @@ sh_fsi2: sound@fe1f0000 {
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interrupts = <0 9 0x4>;
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status = "disabled";
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* External root clock */
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extalr_clk: extalr_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "extalr";
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};
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extal1_clk: extal1_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "extal1";
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};
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extal2_clk: extal2_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "extal2";
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};
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dv_clk: dv_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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clock-output-names = "dv";
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};
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fsiack_clk: fsiack_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "fsiack";
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};
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fsibck_clk: fsibck_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "fsibck";
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};
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/* Special CPG clocks */
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a7740-cpg-clocks";
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reg = <0xe6150000 0x10000>;
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clocks = <&extal1_clk>, <&extalr_clk>;
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#clock-cells = <1>;
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clock-output-names = "system", "pllc0", "pllc1",
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"pllc2", "r",
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"usb24s",
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"i", "zg", "b", "m1", "hp",
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"hpp", "usbp", "s", "zb", "m3",
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"cp";
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};
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/* Variable factor clocks (DIV6) */
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sub_clk: sub_clk@e6150080 {
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compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150080 4>;
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clocks = <&pllc1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sub";
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};
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/* Fixed factor clocks */
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pllc1_div2_clk: pllc1_div2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "pllc1_div2";
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};
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extal1_div2_clk: extal1_div2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&extal1_clk>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "extal1_div2";
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};
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/* Gate clocks */
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subck_clks: subck_clks@e6150080 {
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compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xe6150080 4>;
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clocks = <&sub_clk>, <&sub_clk>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
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>;
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clock-output-names =
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"subck", "subck2";
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};
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mstp1_clks: mstp1_clks@e6150134 {
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compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xe6150134 4>, <0xe6150038 4>;
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clocks = <&cpg_clocks R8A7740_CLK_S>,
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<&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
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<&cpg_clocks R8A7740_CLK_B>,
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<&sub_clk>, <&sub_clk>,
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<&cpg_clocks R8A7740_CLK_B>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
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R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
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R8A7740_CLK_LCDC0
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>;
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clock-output-names =
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"ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
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"tmu1", "lcdc0";
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};
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mstp2_clks: mstp2_clks@e6150138 {
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compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xe6150138 4>, <0xe6150040 4>;
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clocks = <&sub_clk>, <&sub_clk>,
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<&cpg_clocks R8A7740_CLK_HP>,
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<&cpg_clocks R8A7740_CLK_HP>,
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<&cpg_clocks R8A7740_CLK_HP>,
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<&cpg_clocks R8A7740_CLK_HP>,
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<&sub_clk>, <&sub_clk>, <&sub_clk>,
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<&sub_clk>, <&sub_clk>, <&sub_clk>,
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<&sub_clk>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7740_CLK_SCIFA6 R8A7740_CLK_SCIFA7
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R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
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R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
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R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
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R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
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R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
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R8A7740_CLK_SCIFA4
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>;
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clock-output-names =
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"scifa6", "scifa7", "dmac1", "dmac2", "dmac3",
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"usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
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"scifa2", "scifa3", "scifa4";
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};
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mstp3_clks: mstp3_clks@e615013c {
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compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xe615013c 4>, <0xe6150048 4>;
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clocks = <&cpg_clocks R8A7740_CLK_R>,
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<&cpg_clocks R8A7740_CLK_HP>,
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<&sub_clk>,
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<&cpg_clocks R8A7740_CLK_HP>,
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<&cpg_clocks R8A7740_CLK_HP>,
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<&cpg_clocks R8A7740_CLK_HP>,
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<&cpg_clocks R8A7740_CLK_HP>,
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<&cpg_clocks R8A7740_CLK_HP>,
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<&cpg_clocks R8A7740_CLK_HP>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
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R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
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R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
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>;
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clock-output-names =
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"cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
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"mmc", "gether", "tpu0";
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};
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mstp4_clks: mstp4_clks@e6150140 {
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compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xe6150140 4>, <0xe615004c 4>;
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clocks = <&cpg_clocks R8A7740_CLK_HP>,
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<&cpg_clocks R8A7740_CLK_HP>,
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<&cpg_clocks R8A7740_CLK_HP>,
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<&cpg_clocks R8A7740_CLK_HP>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7740_CLK_USBH R8A7740_CLK_SDHI2
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R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
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>;
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clock-output-names =
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"usbhost", "sdhi2", "usbfunc", "usphy";
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};
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};
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};
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