mirror of https://gitee.com/openkylin/linux.git
drm/hisilicon/hibmc: Add support for display engine
Add display engine function, crtc/plane is initialized here. Signed-off-by: Rongrong Zou <zourongrong@gmail.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Reviewed-by: Xinliang Liu <xinliang.liu@linaro.org> Acked-by: Sean Paul <seanpaul@chromium.org>
This commit is contained in:
Rongrong Zou
parent
d1667b8679
commit
da52605eea
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@ -1,4 +1,4 @@
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ccflags-y := -Iinclude/drm
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hibmc-drm-y := hibmc_drm_drv.o hibmc_drm_fbdev.o hibmc_ttm.o
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hibmc-drm-y := hibmc_drm_drv.o hibmc_drm_de.o hibmc_drm_fbdev.o hibmc_ttm.o
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obj-$(CONFIG_DRM_HISI_HIBMC) += hibmc-drm.o
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@ -0,0 +1,477 @@
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/* Hisilicon Hibmc SoC drm driver
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*
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* Based on the bochs drm driver.
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*
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* Copyright (c) 2016 Huawei Limited.
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*
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* Author:
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* Rongrong Zou <zourongrong@huawei.com>
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* Rongrong Zou <zourongrong@gmail.com>
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* Jianhua Li <lijianhua@huawei.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_plane_helper.h>
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#include "hibmc_drm_drv.h"
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#include "hibmc_drm_regs.h"
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struct hibmc_display_panel_pll {
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unsigned long M;
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unsigned long N;
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unsigned long OD;
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unsigned long POD;
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};
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struct hibmc_dislay_pll_config {
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unsigned long hdisplay;
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unsigned long vdisplay;
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u32 pll1_config_value;
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u32 pll2_config_value;
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};
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static const struct hibmc_dislay_pll_config hibmc_pll_table[] = {
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{800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ},
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{1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ},
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{1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ},
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{1280, 768, CRT_PLL1_HS_80MHZ, CRT_PLL2_HS_80MHZ},
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{1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ},
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{1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
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{1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
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{1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ},
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{1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ},
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{1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ},
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};
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#define PADDING(align, data) (((data) + (align) - 1) & (~((align) - 1)))
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static int hibmc_plane_atomic_check(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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struct drm_framebuffer *fb = state->fb;
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struct drm_crtc *crtc = state->crtc;
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struct drm_crtc_state *crtc_state;
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u32 src_w = state->src_w >> 16;
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u32 src_h = state->src_h >> 16;
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if (!crtc || !fb)
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return 0;
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crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
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if (IS_ERR(crtc_state))
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return PTR_ERR(crtc_state);
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if (src_w != state->crtc_w || src_h != state->crtc_h) {
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DRM_DEBUG_ATOMIC("scale not support\n");
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return -EINVAL;
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}
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if (state->crtc_x < 0 || state->crtc_y < 0) {
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DRM_DEBUG_ATOMIC("crtc_x/y of drm_plane state is invalid\n");
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return -EINVAL;
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}
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if (state->crtc_x + state->crtc_w >
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crtc_state->adjusted_mode.hdisplay ||
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state->crtc_y + state->crtc_h >
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crtc_state->adjusted_mode.vdisplay) {
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DRM_DEBUG_ATOMIC("visible portion of plane is invalid\n");
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return -EINVAL;
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}
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return 0;
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}
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static void hibmc_plane_atomic_update(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct drm_plane_state *state = plane->state;
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u32 reg;
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int ret;
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u64 gpu_addr = 0;
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unsigned int line_l;
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struct hibmc_drm_private *priv = plane->dev->dev_private;
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struct hibmc_framebuffer *hibmc_fb;
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struct hibmc_bo *bo;
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if (!state->fb)
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return;
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hibmc_fb = to_hibmc_framebuffer(state->fb);
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bo = gem_to_hibmc_bo(hibmc_fb->obj);
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ret = ttm_bo_reserve(&bo->bo, true, false, NULL);
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if (ret) {
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DRM_ERROR("failed to reserve ttm_bo: %d", ret);
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return;
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}
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ret = hibmc_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
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ttm_bo_unreserve(&bo->bo);
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if (ret) {
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DRM_ERROR("failed to pin hibmc_bo: %d", ret);
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return;
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}
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writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS);
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reg = state->fb->width * (state->fb->bits_per_pixel / 8);
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/* now line_pad is 16 */
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reg = PADDING(16, reg);
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line_l = state->fb->width * state->fb->bits_per_pixel / 8;
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line_l = PADDING(16, line_l);
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writel(HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_WIDTH, reg) |
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HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_OFFS, line_l),
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priv->mmio + HIBMC_CRT_FB_WIDTH);
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/* SET PIXEL FORMAT */
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reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL);
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reg &= ~HIBMC_CRT_DISP_CTL_FORMAT_MASK;
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reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_FORMAT,
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state->fb->bits_per_pixel / 16);
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writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);
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}
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static const u32 channel_formats1[] = {
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DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888,
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DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888,
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DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888,
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DRM_FORMAT_ABGR8888
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};
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static struct drm_plane_funcs hibmc_plane_funcs = {
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.update_plane = drm_atomic_helper_update_plane,
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.disable_plane = drm_atomic_helper_disable_plane,
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.set_property = drm_atomic_helper_plane_set_property,
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.destroy = drm_plane_cleanup,
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.reset = drm_atomic_helper_plane_reset,
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.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
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};
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static const struct drm_plane_helper_funcs hibmc_plane_helper_funcs = {
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.atomic_check = hibmc_plane_atomic_check,
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.atomic_update = hibmc_plane_atomic_update,
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};
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static struct drm_plane *hibmc_plane_init(struct hibmc_drm_private *priv)
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{
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struct drm_device *dev = priv->dev;
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struct drm_plane *plane;
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int ret = 0;
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plane = devm_kzalloc(dev->dev, sizeof(*plane), GFP_KERNEL);
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if (!plane) {
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DRM_ERROR("failed to alloc memory when init plane\n");
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return ERR_PTR(-ENOMEM);
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}
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/*
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* plane init
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* TODO: Now only support primary plane, overlay planes
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* need to do.
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*/
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ret = drm_universal_plane_init(dev, plane, 1, &hibmc_plane_funcs,
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channel_formats1,
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ARRAY_SIZE(channel_formats1),
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DRM_PLANE_TYPE_PRIMARY,
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NULL);
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if (ret) {
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DRM_ERROR("failed to init plane: %d\n", ret);
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return ERR_PTR(ret);
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}
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drm_plane_helper_add(plane, &hibmc_plane_helper_funcs);
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return plane;
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}
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static void hibmc_crtc_enable(struct drm_crtc *crtc)
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{
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unsigned int reg;
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struct hibmc_drm_private *priv = crtc->dev->dev_private;
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hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0);
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/* Enable display power gate & LOCALMEM power gate*/
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reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
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reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
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reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
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reg |= HIBMC_CURR_GATE_LOCALMEM(1);
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reg |= HIBMC_CURR_GATE_DISPLAY(1);
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hibmc_set_current_gate(priv, reg);
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drm_crtc_vblank_on(crtc);
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}
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static void hibmc_crtc_disable(struct drm_crtc *crtc)
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{
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unsigned int reg;
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struct hibmc_drm_private *priv = crtc->dev->dev_private;
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drm_crtc_vblank_off(crtc);
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hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_SLEEP);
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/* Enable display power gate & LOCALMEM power gate*/
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reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
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reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
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reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
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reg |= HIBMC_CURR_GATE_LOCALMEM(0);
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reg |= HIBMC_CURR_GATE_DISPLAY(0);
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hibmc_set_current_gate(priv, reg);
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}
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static unsigned int format_pll_reg(void)
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{
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unsigned int pllreg = 0;
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struct hibmc_display_panel_pll pll = {0};
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/*
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* Note that all PLL's have the same format. Here,
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* we just use Panel PLL parameter to work out the bit
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* fields in the register.On returning a 32 bit number, the value can
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* be applied to any PLL in the calling function.
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*/
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pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_BYPASS, 0);
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pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POWER, 1);
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pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_INPUT, 0);
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pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POD, pll.POD);
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pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_OD, pll.OD);
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pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_N, pll.N);
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pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_M, pll.M);
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return pllreg;
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}
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static void set_vclock_hisilicon(struct drm_device *dev, unsigned long pll)
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{
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u32 val;
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struct hibmc_drm_private *priv = dev->dev_private;
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val = readl(priv->mmio + CRT_PLL1_HS);
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val &= ~(CRT_PLL1_HS_OUTER_BYPASS(1));
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writel(val, priv->mmio + CRT_PLL1_HS);
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val = CRT_PLL1_HS_INTER_BYPASS(1) | CRT_PLL1_HS_POWERON(1);
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writel(val, priv->mmio + CRT_PLL1_HS);
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writel(pll, priv->mmio + CRT_PLL1_HS);
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usleep_range(1000, 2000);
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val = pll & ~(CRT_PLL1_HS_POWERON(1));
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writel(val, priv->mmio + CRT_PLL1_HS);
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usleep_range(1000, 2000);
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val &= ~(CRT_PLL1_HS_INTER_BYPASS(1));
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writel(val, priv->mmio + CRT_PLL1_HS);
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usleep_range(1000, 2000);
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val |= CRT_PLL1_HS_OUTER_BYPASS(1);
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writel(val, priv->mmio + CRT_PLL1_HS);
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}
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static void get_pll_config(unsigned long x, unsigned long y,
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u32 *pll1, u32 *pll2)
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{
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int i;
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int count = ARRAY_SIZE(hibmc_pll_table);
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for (i = 0; i < count; i++) {
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if (hibmc_pll_table[i].hdisplay == x &&
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hibmc_pll_table[i].vdisplay == y) {
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*pll1 = hibmc_pll_table[i].pll1_config_value;
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*pll2 = hibmc_pll_table[i].pll2_config_value;
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return;
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}
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}
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/* if found none, we use default value */
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*pll1 = CRT_PLL1_HS_25MHZ;
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*pll2 = CRT_PLL2_HS_25MHZ;
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}
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/*
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* This function takes care the extra registers and bit fields required to
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* setup a mode in board.
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* Explanation about Display Control register:
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* FPGA only supports 7 predefined pixel clocks, and clock select is
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* in bit 4:0 of new register 0x802a8.
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*/
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static unsigned int display_ctrl_adjust(struct drm_device *dev,
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struct drm_display_mode *mode,
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unsigned int ctrl)
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{
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unsigned long x, y;
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u32 pll1; /* bit[31:0] of PLL */
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u32 pll2; /* bit[63:32] of PLL */
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struct hibmc_drm_private *priv = dev->dev_private;
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x = mode->hdisplay;
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y = mode->vdisplay;
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get_pll_config(x, y, &pll1, &pll2);
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writel(pll2, priv->mmio + CRT_PLL2_HS);
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set_vclock_hisilicon(dev, pll1);
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/*
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* Hisilicon has to set up the top-left and bottom-right
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* registers as well.
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* Note that normal chip only use those two register for
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* auto-centering mode.
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*/
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writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_TOP, 0) |
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HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_LEFT, 0),
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priv->mmio + HIBMC_CRT_AUTO_CENTERING_TL);
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writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM, y - 1) |
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HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_RIGHT, x - 1),
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priv->mmio + HIBMC_CRT_AUTO_CENTERING_BR);
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/*
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* Assume common fields in ctrl have been properly set before
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* calling this function.
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* This function only sets the extra fields in ctrl.
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*/
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/* Set bit 25 of display controller: Select CRT or VGA clock */
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ctrl &= ~HIBMC_CRT_DISP_CTL_CRTSELECT_MASK;
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ctrl &= ~HIBMC_CRT_DISP_CTL_CLOCK_PHASE_MASK;
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ctrl |= HIBMC_CRT_DISP_CTL_CRTSELECT(HIBMC_CRTSELECT_CRT);
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/* clock_phase_polarity is 0 */
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ctrl |= HIBMC_CRT_DISP_CTL_CLOCK_PHASE(0);
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writel(ctrl, priv->mmio + HIBMC_CRT_DISP_CTL);
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return ctrl;
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}
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static void hibmc_crtc_mode_set_nofb(struct drm_crtc *crtc)
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{
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unsigned int val;
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struct drm_display_mode *mode = &crtc->state->mode;
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struct drm_device *dev = crtc->dev;
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struct hibmc_drm_private *priv = dev->dev_private;
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int width = mode->hsync_end - mode->hsync_start;
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int height = mode->vsync_end - mode->vsync_start;
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writel(format_pll_reg(), priv->mmio + HIBMC_CRT_PLL_CTRL);
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writel(HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_TOTAL, mode->htotal - 1) |
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HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_DISP_END, mode->hdisplay - 1),
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priv->mmio + HIBMC_CRT_HORZ_TOTAL);
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writel(HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_WIDTH, width) |
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HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_START, mode->hsync_start - 1),
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priv->mmio + HIBMC_CRT_HORZ_SYNC);
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writel(HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_TOTAL, mode->vtotal - 1) |
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HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_DISP_END, mode->vdisplay - 1),
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priv->mmio + HIBMC_CRT_VERT_TOTAL);
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writel(HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_HEIGHT, height) |
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HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_START, mode->vsync_start - 1),
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priv->mmio + HIBMC_CRT_VERT_SYNC);
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val = HIBMC_FIELD(HIBMC_CRT_DISP_CTL_VSYNC_PHASE, 0);
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val |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_HSYNC_PHASE, 0);
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val |= HIBMC_CRT_DISP_CTL_TIMING(1);
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val |= HIBMC_CRT_DISP_CTL_PLANE(1);
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display_ctrl_adjust(dev, mode, val);
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}
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static void hibmc_crtc_atomic_begin(struct drm_crtc *crtc,
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struct drm_crtc_state *old_state)
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{
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unsigned int reg;
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struct drm_device *dev = crtc->dev;
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struct hibmc_drm_private *priv = dev->dev_private;
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hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0);
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|
||||
/* Enable display power gate & LOCALMEM power gate*/
|
||||
reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
|
||||
reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
|
||||
reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
|
||||
reg |= HIBMC_CURR_GATE_DISPLAY(1);
|
||||
reg |= HIBMC_CURR_GATE_LOCALMEM(1);
|
||||
hibmc_set_current_gate(priv, reg);
|
||||
|
||||
/* We can add more initialization as needed. */
|
||||
}
|
||||
|
||||
static void hibmc_crtc_atomic_flush(struct drm_crtc *crtc,
|
||||
struct drm_crtc_state *old_state)
|
||||
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&crtc->dev->event_lock, flags);
|
||||
if (crtc->state->event)
|
||||
drm_crtc_send_vblank_event(crtc, crtc->state->event);
|
||||
crtc->state->event = NULL;
|
||||
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
|
||||
}
|
||||
|
||||
static const struct drm_crtc_funcs hibmc_crtc_funcs = {
|
||||
.page_flip = drm_atomic_helper_page_flip,
|
||||
.set_config = drm_atomic_helper_set_config,
|
||||
.destroy = drm_crtc_cleanup,
|
||||
.reset = drm_atomic_helper_crtc_reset,
|
||||
.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
|
||||
.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
|
||||
};
|
||||
|
||||
static const struct drm_crtc_helper_funcs hibmc_crtc_helper_funcs = {
|
||||
.enable = hibmc_crtc_enable,
|
||||
.disable = hibmc_crtc_disable,
|
||||
.mode_set_nofb = hibmc_crtc_mode_set_nofb,
|
||||
.atomic_begin = hibmc_crtc_atomic_begin,
|
||||
.atomic_flush = hibmc_crtc_atomic_flush,
|
||||
};
|
||||
|
||||
int hibmc_de_init(struct hibmc_drm_private *priv)
|
||||
{
|
||||
struct drm_device *dev = priv->dev;
|
||||
struct drm_crtc *crtc;
|
||||
struct drm_plane *plane;
|
||||
int ret;
|
||||
|
||||
plane = hibmc_plane_init(priv);
|
||||
if (IS_ERR(plane)) {
|
||||
DRM_ERROR("failed to create plane: %ld\n", PTR_ERR(plane));
|
||||
return PTR_ERR(plane);
|
||||
}
|
||||
|
||||
crtc = devm_kzalloc(dev->dev, sizeof(*crtc), GFP_KERNEL);
|
||||
if (!crtc) {
|
||||
DRM_ERROR("failed to alloc memory when init crtc\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ret = drm_crtc_init_with_planes(dev, crtc, plane,
|
||||
NULL, &hibmc_crtc_funcs, NULL);
|
||||
if (ret) {
|
||||
DRM_ERROR("failed to init crtc: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = drm_mode_crtc_set_gamma_size(crtc, 256);
|
||||
if (ret) {
|
||||
DRM_ERROR("failed to set gamma size: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
drm_crtc_helper_add(crtc, &hibmc_crtc_helper_funcs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -19,6 +19,9 @@
|
|||
#include <linux/console.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <drm/drm_atomic_helper.h>
|
||||
#include <drm/drm_crtc_helper.h>
|
||||
|
||||
#include "hibmc_drm_drv.h"
|
||||
#include "hibmc_drm_regs.h"
|
||||
|
||||
|
|
@ -44,7 +47,8 @@ static void hibmc_disable_vblank(struct drm_device *dev, unsigned int pipe)
|
|||
}
|
||||
|
||||
static struct drm_driver hibmc_driver = {
|
||||
.driver_features = DRIVER_GEM,
|
||||
.driver_features = DRIVER_GEM | DRIVER_MODESET |
|
||||
DRIVER_ATOMIC,
|
||||
.fops = &hibmc_fops,
|
||||
.name = "hibmc",
|
||||
.date = "20160828",
|
||||
|
|
@ -62,11 +66,31 @@ static struct drm_driver hibmc_driver = {
|
|||
|
||||
static int hibmc_pm_suspend(struct device *dev)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(dev);
|
||||
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
||||
struct hibmc_drm_private *priv = drm_dev->dev_private;
|
||||
|
||||
drm_kms_helper_poll_disable(drm_dev);
|
||||
priv->suspend_state = drm_atomic_helper_suspend(drm_dev);
|
||||
if (IS_ERR(priv->suspend_state)) {
|
||||
DRM_ERROR("drm_atomic_helper_suspend failed: %ld\n",
|
||||
PTR_ERR(priv->suspend_state));
|
||||
drm_kms_helper_poll_enable(drm_dev);
|
||||
return PTR_ERR(priv->suspend_state);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hibmc_pm_resume(struct device *dev)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(dev);
|
||||
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
||||
struct hibmc_drm_private *priv = drm_dev->dev_private;
|
||||
|
||||
drm_atomic_helper_resume(drm_dev, priv->suspend_state);
|
||||
drm_kms_helper_poll_enable(drm_dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -75,6 +99,41 @@ static const struct dev_pm_ops hibmc_pm_ops = {
|
|||
hibmc_pm_resume)
|
||||
};
|
||||
|
||||
static int hibmc_kms_init(struct hibmc_drm_private *priv)
|
||||
{
|
||||
int ret;
|
||||
|
||||
drm_mode_config_init(priv->dev);
|
||||
priv->mode_config_initialized = true;
|
||||
|
||||
priv->dev->mode_config.min_width = 0;
|
||||
priv->dev->mode_config.min_height = 0;
|
||||
priv->dev->mode_config.max_width = 1920;
|
||||
priv->dev->mode_config.max_height = 1440;
|
||||
|
||||
priv->dev->mode_config.fb_base = priv->fb_base;
|
||||
priv->dev->mode_config.preferred_depth = 24;
|
||||
priv->dev->mode_config.prefer_shadow = 0;
|
||||
|
||||
priv->dev->mode_config.funcs = (void *)&hibmc_mode_funcs;
|
||||
|
||||
ret = hibmc_de_init(priv);
|
||||
if (ret) {
|
||||
DRM_ERROR("failed to init de: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void hibmc_kms_fini(struct hibmc_drm_private *priv)
|
||||
{
|
||||
if (priv->mode_config_initialized) {
|
||||
drm_mode_config_cleanup(priv->dev);
|
||||
priv->mode_config_initialized = false;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* It can operate in one of three modes: 0, 1 or Sleep.
|
||||
*/
|
||||
|
|
@ -203,6 +262,7 @@ static int hibmc_unload(struct drm_device *dev)
|
|||
struct hibmc_drm_private *priv = dev->dev_private;
|
||||
|
||||
hibmc_fbdev_fini(priv);
|
||||
hibmc_kms_fini(priv);
|
||||
hibmc_mm_fini(priv);
|
||||
dev->dev_private = NULL;
|
||||
return 0;
|
||||
|
|
@ -229,6 +289,13 @@ static int hibmc_load(struct drm_device *dev)
|
|||
if (ret)
|
||||
goto err;
|
||||
|
||||
ret = hibmc_kms_init(priv);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
/* reset all the states of crtc/plane/encoder/connector */
|
||||
drm_mode_config_reset(dev);
|
||||
|
||||
ret = hibmc_fbdev_init(priv);
|
||||
if (ret) {
|
||||
DRM_ERROR("failed to initialize fbdev: %d\n", ret);
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#define HIBMC_DRM_DRV_H
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/drm_atomic.h>
|
||||
#include <drm/drm_fb_helper.h>
|
||||
#include <drm/drm_gem.h>
|
||||
#include <drm/ttm/ttm_bo_driver.h>
|
||||
|
|
@ -44,6 +45,8 @@ struct hibmc_drm_private {
|
|||
|
||||
/* drm */
|
||||
struct drm_device *dev;
|
||||
bool mode_config_initialized;
|
||||
struct drm_atomic_state *suspend_state;
|
||||
|
||||
/* ttm */
|
||||
struct drm_global_reference mem_global_ref;
|
||||
|
|
@ -82,6 +85,7 @@ void hibmc_set_power_mode(struct hibmc_drm_private *priv,
|
|||
void hibmc_set_current_gate(struct hibmc_drm_private *priv,
|
||||
unsigned int gate);
|
||||
|
||||
int hibmc_de_init(struct hibmc_drm_private *priv);
|
||||
int hibmc_fbdev_init(struct hibmc_drm_private *priv);
|
||||
void hibmc_fbdev_fini(struct hibmc_drm_private *priv);
|
||||
|
||||
|
|
@ -103,4 +107,6 @@ int hibmc_dumb_mmap_offset(struct drm_file *file, struct drm_device *dev,
|
|||
u32 handle, u64 *offset);
|
||||
int hibmc_mmap(struct file *filp, struct vm_area_struct *vma);
|
||||
|
||||
extern const struct drm_mode_config_funcs hibmc_mode_funcs;
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -550,3 +550,9 @@ hibmc_user_framebuffer_create(struct drm_device *dev,
|
|||
}
|
||||
return &hibmc_fb->fb;
|
||||
}
|
||||
|
||||
const struct drm_mode_config_funcs hibmc_mode_funcs = {
|
||||
.atomic_check = drm_atomic_helper_check,
|
||||
.atomic_commit = drm_atomic_helper_commit,
|
||||
.fb_create = hibmc_user_framebuffer_create,
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue